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-rw-r--r--src/soc/intel/tigerlake/graphics.c30
1 files changed, 0 insertions, 30 deletions
diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c
index ea90d44033..11aea72211 100644
--- a/src/soc/intel/tigerlake/graphics.c
+++ b/src/soc/intel/tigerlake/graphics.c
@@ -6,12 +6,7 @@
* Chapter number: 4
*/
-#include <console/console.h>
#include <fsp/util.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <drivers/intel/gma/opregion.h>
#include <intelblocks/graphics.h>
#include <types.h>
@@ -19,28 +14,3 @@ uintptr_t fsp_soc_get_igd_bar(void)
{
return graphics_get_memory_base();
}
-
-void graphics_soc_init(struct device *dev)
-{
- intel_gma_init_igd_opregion();
-
- /*
- * GFX PEIM module inside FSP binary is taking care of graphics
- * initialization based on RUN_FSP_GOP Kconfig
- * option and input VBT file. Hence no need to load/execute legacy VGA
- * OpROM in order to initialize GFX.
- *
- * In case of non-FSP solution, SoC need to select VGA_ROM_RUN
- * Kconfig to perform GFX initialization through VGA OpRom.
- */
- if (CONFIG(RUN_FSP_GOP))
- return;
-
- /* IGD needs to Bus Master */
- uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* Initialize PCI device, load/execute BIOS Option ROM */
- pci_dev_init(dev);
-}