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-rw-r--r--src/soc/intel/tigerlake/acpi.c1
-rw-r--r--src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/gpio.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/gpio_op.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/ipu.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/ish.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/pch_glan.asl3
-rw-r--r--src/soc/intel/tigerlake/acpi/pch_hda.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/pci_irqs.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/pcie.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/platform.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/pmc.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/scs.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/serialio.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/smbus.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/southbridge.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/xhci.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/xhci_jsl.asl1
-rw-r--r--src/soc/intel/tigerlake/acpi/xhci_tgl.asl1
-rw-r--r--src/soc/intel/tigerlake/bootblock/bootblock.c1
-rw-r--r--src/soc/intel/tigerlake/bootblock/cpu.c1
-rw-r--r--src/soc/intel/tigerlake/bootblock/pch.c1
-rw-r--r--src/soc/intel/tigerlake/bootblock/report_platform.c1
-rw-r--r--src/soc/intel/tigerlake/chip.c1
-rw-r--r--src/soc/intel/tigerlake/chip.h1
-rw-r--r--src/soc/intel/tigerlake/cpu.c1
-rw-r--r--src/soc/intel/tigerlake/elog.c2
-rw-r--r--src/soc/intel/tigerlake/espi.c1
-rw-r--r--src/soc/intel/tigerlake/finalize.c1
-rw-r--r--src/soc/intel/tigerlake/fsp_params_jsl.c1
-rw-r--r--src/soc/intel/tigerlake/fsp_params_tgl.c1
-rw-r--r--src/soc/intel/tigerlake/gpio_jsl.c1
-rw-r--r--src/soc/intel/tigerlake/gpio_tgl.c1
-rw-r--r--src/soc/intel/tigerlake/graphics.c1
-rw-r--r--src/soc/intel/tigerlake/gspi.c1
-rw-r--r--src/soc/intel/tigerlake/i2c.c1
-rw-r--r--src/soc/intel/tigerlake/include/soc/bootblock.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/cpu.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/espi.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/gpe.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/gpio.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/gpio_defs.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/iomap.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/irq.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/irq_jsl.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/irq_tgl.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/itss.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/me.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/meminit_jsl.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/meminit_tgl.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/msr.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/nvs.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/p2sb.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/pch.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/pci_devs.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/pcr_ids.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/pm.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/pmc.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/ramstage.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/romstage.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/serialio.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/smbus.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/soc_chip.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/systemagent.h1
-rw-r--r--src/soc/intel/tigerlake/include/soc/usb.h1
-rw-r--r--src/soc/intel/tigerlake/lockdown.c1
-rw-r--r--src/soc/intel/tigerlake/meminit_jsl.c1
-rw-r--r--src/soc/intel/tigerlake/meminit_tgl.c1
-rw-r--r--src/soc/intel/tigerlake/p2sb.c1
-rw-r--r--src/soc/intel/tigerlake/pmc.c1
-rw-r--r--src/soc/intel/tigerlake/pmutil.c1
-rw-r--r--src/soc/intel/tigerlake/reset.c1
-rw-r--r--src/soc/intel/tigerlake/romstage/Makefile.inc1
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params_jsl.c1
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params_tgl.c1
-rw-r--r--src/soc/intel/tigerlake/romstage/pch.c1
-rw-r--r--src/soc/intel/tigerlake/romstage/romstage.c1
-rw-r--r--src/soc/intel/tigerlake/romstage/systemagent.c1
-rw-r--r--src/soc/intel/tigerlake/sd.c1
-rw-r--r--src/soc/intel/tigerlake/smihandler.c1
-rw-r--r--src/soc/intel/tigerlake/smmrelocate.c1
-rw-r--r--src/soc/intel/tigerlake/spi.c1
-rw-r--r--src/soc/intel/tigerlake/systemagent.c1
-rw-r--r--src/soc/intel/tigerlake/uart.c1
91 files changed, 0 insertions, 94 deletions
diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c
index af4076cf60..23fd970500 100644
--- a/src/soc/intel/tigerlake/acpi.c
+++ b/src/soc/intel/tigerlake/acpi.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019-2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl
index c9da977c7d..4f08cd78bd 100644
--- a/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl
+++ b/src/soc/intel/tigerlake/acpi/camera_clock_ctl.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl
index 0378b52be3..9bf0c6032f 100644
--- a/src/soc/intel/tigerlake/acpi/gpio.asl
+++ b/src/soc/intel/tigerlake/acpi/gpio.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/gpio_op.asl b/src/soc/intel/tigerlake/acpi/gpio_op.asl
index a16ebf753d..4444c09a5b 100644
--- a/src/soc/intel/tigerlake/acpi/gpio_op.asl
+++ b/src/soc/intel/tigerlake/acpi/gpio_op.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/ipu.asl b/src/soc/intel/tigerlake/acpi/ipu.asl
index ed964a4165..5711644bcb 100644
--- a/src/soc/intel/tigerlake/acpi/ipu.asl
+++ b/src/soc/intel/tigerlake/acpi/ipu.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/ish.asl b/src/soc/intel/tigerlake/acpi/ish.asl
index 186a147f44..ee3f1a3fdf 100644
--- a/src/soc/intel/tigerlake/acpi/ish.asl
+++ b/src/soc/intel/tigerlake/acpi/ish.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2019 Google LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/pch_glan.asl b/src/soc/intel/tigerlake/acpi/pch_glan.asl
index 260dd44962..2d9d960565 100644
--- a/src/soc/intel/tigerlake/acpi/pch_glan.asl
+++ b/src/soc/intel/tigerlake/acpi/pch_glan.asl
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2017-2108 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/pch_hda.asl b/src/soc/intel/tigerlake/acpi/pch_hda.asl
index 708d0b56f1..0d10d2deb5 100644
--- a/src/soc/intel/tigerlake/acpi/pch_hda.asl
+++ b/src/soc/intel/tigerlake/acpi/pch_hda.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl
index d3230b4aa9..7048c150f6 100644
--- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl
+++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl b/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl
index 006a5de4a8..086282e733 100644
--- a/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl
+++ b/src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl b/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl
index 8aadf8db6a..7f632ba32e 100644
--- a/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl
+++ b/src/soc/intel/tigerlake/acpi/pci_irqs_tgl.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl
index c6cfbce57b..53ae316413 100644
--- a/src/soc/intel/tigerlake/acpi/pcie.asl
+++ b/src/soc/intel/tigerlake/acpi/pcie.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/platform.asl b/src/soc/intel/tigerlake/acpi/platform.asl
index dde9b13186..682a7b93d8 100644
--- a/src/soc/intel/tigerlake/acpi/platform.asl
+++ b/src/soc/intel/tigerlake/acpi/platform.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/pmc.asl b/src/soc/intel/tigerlake/acpi/pmc.asl
index 0d62edd926..6dd2d35354 100644
--- a/src/soc/intel/tigerlake/acpi/pmc.asl
+++ b/src/soc/intel/tigerlake/acpi/pmc.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/scs.asl b/src/soc/intel/tigerlake/acpi/scs.asl
index a9ff93c2ca..83da7e0f06 100644
--- a/src/soc/intel/tigerlake/acpi/scs.asl
+++ b/src/soc/intel/tigerlake/acpi/scs.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/serialio.asl b/src/soc/intel/tigerlake/acpi/serialio.asl
index 95759c2dd0..6fd135b437 100644
--- a/src/soc/intel/tigerlake/acpi/serialio.asl
+++ b/src/soc/intel/tigerlake/acpi/serialio.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/smbus.asl b/src/soc/intel/tigerlake/acpi/smbus.asl
index 8febe9deef..f273e3669d 100644
--- a/src/soc/intel/tigerlake/acpi/smbus.asl
+++ b/src/soc/intel/tigerlake/acpi/smbus.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl
index 1403eb4b13..adb16aa4ba 100644
--- a/src/soc/intel/tigerlake/acpi/southbridge.asl
+++ b/src/soc/intel/tigerlake/acpi/southbridge.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019-2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/xhci.asl b/src/soc/intel/tigerlake/acpi/xhci.asl
index 9618cf3003..f147a2a83f 100644
--- a/src/soc/intel/tigerlake/acpi/xhci.asl
+++ b/src/soc/intel/tigerlake/acpi/xhci.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/xhci_jsl.asl b/src/soc/intel/tigerlake/acpi/xhci_jsl.asl
index fe17b0d1bf..41be89ace1 100644
--- a/src/soc/intel/tigerlake/acpi/xhci_jsl.asl
+++ b/src/soc/intel/tigerlake/acpi/xhci_jsl.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/acpi/xhci_tgl.asl b/src/soc/intel/tigerlake/acpi/xhci_tgl.asl
index 312cc5a88e..b97f52052b 100644
--- a/src/soc/intel/tigerlake/acpi/xhci_tgl.asl
+++ b/src/soc/intel/tigerlake/acpi/xhci_tgl.asl
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c
index a4f965947d..1abca127a3 100644
--- a/src/soc/intel/tigerlake/bootblock/bootblock.c
+++ b/src/soc/intel/tigerlake/bootblock/bootblock.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/bootblock/cpu.c b/src/soc/intel/tigerlake/bootblock/cpu.c
index 1bae4fa804..dddf24352d 100644
--- a/src/soc/intel/tigerlake/bootblock/cpu.c
+++ b/src/soc/intel/tigerlake/bootblock/cpu.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 090f88f910..b0646018c6 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c
index c6a62c3deb..d7b2e0db32 100644
--- a/src/soc/intel/tigerlake/bootblock/report_platform.c
+++ b/src/soc/intel/tigerlake/bootblock/report_platform.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index dc36da34c4..1c7078d6cf 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 87aa8943e4..f82f13d45b 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c
index cfbfdb3ea4..dfbcd22b94 100644
--- a/src/soc/intel/tigerlake/cpu.c
+++ b/src/soc/intel/tigerlake/cpu.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c
index 2ec6b410df..903259497d 100644
--- a/src/soc/intel/tigerlake/elog.c
+++ b/src/soc/intel/tigerlake/elog.c
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2015 Intel Corporation.
- * Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c
index 7efd210cad..da36ea6304 100644
--- a/src/soc/intel/tigerlake/espi.c
+++ b/src/soc/intel/tigerlake/espi.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c
index aed5cc0e5e..b636ccbec0 100644
--- a/src/soc/intel/tigerlake/finalize.c
+++ b/src/soc/intel/tigerlake/finalize.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c
index 96aa7ba016..932bd06ff7 100644
--- a/src/soc/intel/tigerlake/fsp_params_jsl.c
+++ b/src/soc/intel/tigerlake/fsp_params_jsl.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019-2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index 33abac4411..f3f700f146 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/gpio_jsl.c b/src/soc/intel/tigerlake/gpio_jsl.c
index bd0f5004b6..afb9f7b3bc 100644
--- a/src/soc/intel/tigerlake/gpio_jsl.c
+++ b/src/soc/intel/tigerlake/gpio_jsl.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/gpio_tgl.c b/src/soc/intel/tigerlake/gpio_tgl.c
index 54ed5d3f92..cfdd0ac465 100644
--- a/src/soc/intel/tigerlake/gpio_tgl.c
+++ b/src/soc/intel/tigerlake/gpio_tgl.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c
index c215384f10..fef17e17e8 100644
--- a/src/soc/intel/tigerlake/graphics.c
+++ b/src/soc/intel/tigerlake/graphics.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/gspi.c b/src/soc/intel/tigerlake/gspi.c
index 2dc738ec97..1381fb2499 100644
--- a/src/soc/intel/tigerlake/gspi.c
+++ b/src/soc/intel/tigerlake/gspi.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/i2c.c b/src/soc/intel/tigerlake/i2c.c
index 3d00372d59..46bc726726 100644
--- a/src/soc/intel/tigerlake/i2c.c
+++ b/src/soc/intel/tigerlake/i2c.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/bootblock.h b/src/soc/intel/tigerlake/include/soc/bootblock.h
index 6dbbfecd02..0c8d8c201a 100644
--- a/src/soc/intel/tigerlake/include/soc/bootblock.h
+++ b/src/soc/intel/tigerlake/include/soc/bootblock.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/cpu.h b/src/soc/intel/tigerlake/include/soc/cpu.h
index 210e6993ed..799382498b 100644
--- a/src/soc/intel/tigerlake/include/soc/cpu.h
+++ b/src/soc/intel/tigerlake/include/soc/cpu.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/espi.h b/src/soc/intel/tigerlake/include/soc/espi.h
index 03cf8e8b55..3f7e32a717 100644
--- a/src/soc/intel/tigerlake/include/soc/espi.h
+++ b/src/soc/intel/tigerlake/include/soc/espi.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/gpe.h b/src/soc/intel/tigerlake/include/soc/gpe.h
index d946e2af13..c37750b1c4 100644
--- a/src/soc/intel/tigerlake/include/soc/gpe.h
+++ b/src/soc/intel/tigerlake/include/soc/gpe.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h
index 3a39e3a153..7a6df7c74f 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h
index db5b3741cd..07835aac2d 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h b/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h
index c2d686366d..69ed539cae 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio_defs_jsl.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h b/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h
index 7017aa8e87..35a15ded66 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio_defs_tgl.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
index 145892b7d1..28551ba28a 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h
index ce7d0d87e5..6cfb1873cb 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_jsl.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h
index 750f589689..ec582c3133 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs_tgl.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h
index d9fc01eaa8..361c296547 100644
--- a/src/soc/intel/tigerlake/include/soc/iomap.h
+++ b/src/soc/intel/tigerlake/include/soc/iomap.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019-2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h
index dec8376033..b87467ad5b 100644
--- a/src/soc/intel/tigerlake/include/soc/irq.h
+++ b/src/soc/intel/tigerlake/include/soc/irq.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/irq_jsl.h b/src/soc/intel/tigerlake/include/soc/irq_jsl.h
index 2a2d20f671..a6edd23d97 100644
--- a/src/soc/intel/tigerlake/include/soc/irq_jsl.h
+++ b/src/soc/intel/tigerlake/include/soc/irq_jsl.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/irq_tgl.h b/src/soc/intel/tigerlake/include/soc/irq_tgl.h
index 0ea6053c2d..6f268c1eae 100644
--- a/src/soc/intel/tigerlake/include/soc/irq_tgl.h
+++ b/src/soc/intel/tigerlake/include/soc/irq_tgl.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/itss.h b/src/soc/intel/tigerlake/include/soc/itss.h
index 6631ccc27d..39794ead73 100644
--- a/src/soc/intel/tigerlake/include/soc/itss.h
+++ b/src/soc/intel/tigerlake/include/soc/itss.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/me.h b/src/soc/intel/tigerlake/include/soc/me.h
index 9bb41ca57b..94331b4c9e 100644
--- a/src/soc/intel/tigerlake/include/soc/me.h
+++ b/src/soc/intel/tigerlake/include/soc/me.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h
index 588ad5c58d..7f860ede52 100644
--- a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h
+++ b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h
index dd0541809e..5573fb7110 100644
--- a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h
+++ b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
diff --git a/src/soc/intel/tigerlake/include/soc/msr.h b/src/soc/intel/tigerlake/include/soc/msr.h
index 2aa79af3d7..7925ea76b0 100644
--- a/src/soc/intel/tigerlake/include/soc/msr.h
+++ b/src/soc/intel/tigerlake/include/soc/msr.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/nvs.h b/src/soc/intel/tigerlake/include/soc/nvs.h
index c855df0305..cfb189d381 100644
--- a/src/soc/intel/tigerlake/include/soc/nvs.h
+++ b/src/soc/intel/tigerlake/include/soc/nvs.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/p2sb.h b/src/soc/intel/tigerlake/include/soc/p2sb.h
index 46fdf47c59..d483ee399b 100644
--- a/src/soc/intel/tigerlake/include/soc/p2sb.h
+++ b/src/soc/intel/tigerlake/include/soc/p2sb.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/pch.h b/src/soc/intel/tigerlake/include/soc/pch.h
index ae8e310afb..c2f497c1c8 100644
--- a/src/soc/intel/tigerlake/include/soc/pch.h
+++ b/src/soc/intel/tigerlake/include/soc/pch.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h
index af449ba118..8b740cf93b 100644
--- a/src/soc/intel/tigerlake/include/soc/pci_devs.h
+++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019-2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/pcr_ids.h b/src/soc/intel/tigerlake/include/soc/pcr_ids.h
index 16162d9ecc..4143892f87 100644
--- a/src/soc/intel/tigerlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/tigerlake/include/soc/pcr_ids.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h
index 588dfba7ba..14fa5d0c08 100644
--- a/src/soc/intel/tigerlake/include/soc/pm.h
+++ b/src/soc/intel/tigerlake/include/soc/pm.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h
index 53076e5885..10693c02a9 100644
--- a/src/soc/intel/tigerlake/include/soc/pmc.h
+++ b/src/soc/intel/tigerlake/include/soc/pmc.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/ramstage.h b/src/soc/intel/tigerlake/include/soc/ramstage.h
index 606e2ffb8d..a8c8fdd7b2 100644
--- a/src/soc/intel/tigerlake/include/soc/ramstage.h
+++ b/src/soc/intel/tigerlake/include/soc/ramstage.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h
index 98ed6bc158..1672e8b5ca 100644
--- a/src/soc/intel/tigerlake/include/soc/romstage.h
+++ b/src/soc/intel/tigerlake/include/soc/romstage.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/serialio.h b/src/soc/intel/tigerlake/include/soc/serialio.h
index 04c0efe19b..509f0b0f14 100644
--- a/src/soc/intel/tigerlake/include/soc/serialio.h
+++ b/src/soc/intel/tigerlake/include/soc/serialio.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/smbus.h b/src/soc/intel/tigerlake/include/soc/smbus.h
index 0ad565a613..3fb8291698 100644
--- a/src/soc/intel/tigerlake/include/soc/smbus.h
+++ b/src/soc/intel/tigerlake/include/soc/smbus.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/soc_chip.h b/src/soc/intel/tigerlake/include/soc/soc_chip.h
index 3b02386375..250aa9a0aa 100644
--- a/src/soc/intel/tigerlake/include/soc/soc_chip.h
+++ b/src/soc/intel/tigerlake/include/soc/soc_chip.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h
index 92d70723df..d8c8ad47da 100644
--- a/src/soc/intel/tigerlake/include/soc/systemagent.h
+++ b/src/soc/intel/tigerlake/include/soc/systemagent.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019-2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/include/soc/usb.h b/src/soc/intel/tigerlake/include/soc/usb.h
index d2e50ef1e8..33c0bf0bf9 100644
--- a/src/soc/intel/tigerlake/include/soc/usb.h
+++ b/src/soc/intel/tigerlake/include/soc/usb.h
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/lockdown.c b/src/soc/intel/tigerlake/lockdown.c
index 08ae4ef455..18d4fa728e 100644
--- a/src/soc/intel/tigerlake/lockdown.c
+++ b/src/soc/intel/tigerlake/lockdown.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/meminit_jsl.c b/src/soc/intel/tigerlake/meminit_jsl.c
index f977ce2cc3..3247357f1a 100644
--- a/src/soc/intel/tigerlake/meminit_jsl.c
+++ b/src/soc/intel/tigerlake/meminit_jsl.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/meminit_tgl.c b/src/soc/intel/tigerlake/meminit_tgl.c
index 922f66a543..a0e5107998 100644
--- a/src/soc/intel/tigerlake/meminit_tgl.c
+++ b/src/soc/intel/tigerlake/meminit_tgl.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2020 The coreboot project Authors.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
diff --git a/src/soc/intel/tigerlake/p2sb.c b/src/soc/intel/tigerlake/p2sb.c
index f5a3e70fce..64f181f634 100644
--- a/src/soc/intel/tigerlake/p2sb.c
+++ b/src/soc/intel/tigerlake/p2sb.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c
index 65284ec57c..13902b80a6 100644
--- a/src/soc/intel/tigerlake/pmc.c
+++ b/src/soc/intel/tigerlake/pmc.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c
index d9eb18665e..ac254020cb 100644
--- a/src/soc/intel/tigerlake/pmutil.c
+++ b/src/soc/intel/tigerlake/pmutil.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/reset.c b/src/soc/intel/tigerlake/reset.c
index 11e411da48..431a70ccb0 100644
--- a/src/soc/intel/tigerlake/reset.c
+++ b/src/soc/intel/tigerlake/reset.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc
index 2bf9812c08..817df541a9 100644
--- a/src/soc/intel/tigerlake/romstage/Makefile.inc
+++ b/src/soc/intel/tigerlake/romstage/Makefile.inc
@@ -1,7 +1,6 @@
#
# This file is part of the coreboot project.
#
-# Copyright (C) 2019 Intel Corporation
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
index a5c4c907e2..39fc445b90 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019-2020 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index b46f3a3f10..e275e59fcc 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019-2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/romstage/pch.c b/src/soc/intel/tigerlake/romstage/pch.c
index 88a7cc7163..a005ea0b99 100644
--- a/src/soc/intel/tigerlake/romstage/pch.c
+++ b/src/soc/intel/tigerlake/romstage/pch.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c
index f592bb0574..f78ea29ae1 100644
--- a/src/soc/intel/tigerlake/romstage/romstage.c
+++ b/src/soc/intel/tigerlake/romstage/romstage.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/romstage/systemagent.c b/src/soc/intel/tigerlake/romstage/systemagent.c
index 183089e9fb..9fa498e802 100644
--- a/src/soc/intel/tigerlake/romstage/systemagent.c
+++ b/src/soc/intel/tigerlake/romstage/systemagent.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/sd.c b/src/soc/intel/tigerlake/sd.c
index bc9dd9b26f..9898734f3d 100644
--- a/src/soc/intel/tigerlake/sd.c
+++ b/src/soc/intel/tigerlake/sd.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c
index 1eb56aac8d..67e59a26a0 100644
--- a/src/soc/intel/tigerlake/smihandler.c
+++ b/src/soc/intel/tigerlake/smihandler.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019-2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c
index 9e21a233a3..44b464441d 100644
--- a/src/soc/intel/tigerlake/smmrelocate.c
+++ b/src/soc/intel/tigerlake/smmrelocate.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/spi.c b/src/soc/intel/tigerlake/spi.c
index df4a593368..5270616af6 100644
--- a/src/soc/intel/tigerlake/spi.c
+++ b/src/soc/intel/tigerlake/spi.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c
index 152f8f90d9..fb0ce118aa 100644
--- a/src/soc/intel/tigerlake/systemagent.c
+++ b/src/soc/intel/tigerlake/systemagent.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019-2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/src/soc/intel/tigerlake/uart.c b/src/soc/intel/tigerlake/uart.c
index b330e7791a..03b4469a98 100644
--- a/src/soc/intel/tigerlake/uart.c
+++ b/src/soc/intel/tigerlake/uart.c
@@ -1,7 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by