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-rw-r--r--src/soc/intel/tigerlake/Makefile.inc1
-rw-r--r--src/soc/intel/tigerlake/me.c19
2 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc
index fd2464d505..4aa1f2f4d1 100644
--- a/src/soc/intel/tigerlake/Makefile.inc
+++ b/src/soc/intel/tigerlake/Makefile.inc
@@ -44,6 +44,7 @@ ramstage-y += reset.c
ramstage-y += smmrelocate.c
ramstage-y += systemagent.c
ramstage-y += sd.c
+ramstage-y += me.c
smm-y += gpio.c
smm-y += p2sb.c
diff --git a/src/soc/intel/tigerlake/me.c b/src/soc/intel/tigerlake/me.c
new file mode 100644
index 0000000000..d48b32bf6b
--- /dev/null
+++ b/src/soc/intel/tigerlake/me.c
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Google LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootstate.h>
+#include <intelblocks/cse.h>
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL);