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Diffstat (limited to 'src/soc/intel/xeon_sp/include/soc/ramstage.h')
-rw-r--r--src/soc/intel/xeon_sp/include/soc/ramstage.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/ramstage.h b/src/soc/intel/xeon_sp/include/soc/ramstage.h
new file mode 100644
index 0000000000..18373f8884
--- /dev/null
+++ b/src/soc/intel/xeon_sp/include/soc/ramstage.h
@@ -0,0 +1,17 @@
+/* This file is part of the coreboot project. */
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <device/device.h>
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <memory_info.h>
+
+void xeon_sp_init_cpus(struct device *dev);
+void mainboard_silicon_init_params(FSPS_UPD *params);
+
+extern struct pci_operations soc_pci_ops;
+
+#endif