summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/acpi.c2
-rw-r--r--src/soc/intel/apollolake/chip.c2
-rw-r--r--src/soc/intel/apollolake/nhlt.c6
-rw-r--r--src/soc/intel/baytrail/gpio.c2
-rw-r--r--src/soc/intel/baytrail/pmutil.c2
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c4
-rw-r--r--src/soc/intel/cannonlake/cbmem.c2
-rw-r--r--src/soc/intel/cannonlake/nhlt.c2
-rw-r--r--src/soc/intel/common/block/systemagent/systemagent.c4
-rw-r--r--src/soc/intel/fsp_baytrail/gpio.c4
-rw-r--r--src/soc/intel/skylake/acpi/dptf/thermal.asl40
-rw-r--r--src/soc/intel/skylake/acpi/xhci.asl4
-rw-r--r--src/soc/intel/skylake/nhlt/max98373.c2
13 files changed, 38 insertions, 38 deletions
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index bf93ef40a8..9226ac3bd1 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -174,7 +174,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
}
- cfg = dev->chip_info;
+ cfg = dev->chip_info;
if(cfg->lpss_s0ix_enable)
fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 4ea89710ab..ba10e35562 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -573,7 +573,7 @@ static void glk_fsp_silicon_init_params_cb(
void __weak mainboard_devtree_update(struct device *dev)
{
- /* Override dev tree settings per board */
+ /* Override dev tree settings per board */
}
void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
diff --git a/src/soc/intel/apollolake/nhlt.c b/src/soc/intel/apollolake/nhlt.c
index a46b188a95..6a71f1ee7e 100644
--- a/src/soc/intel/apollolake/nhlt.c
+++ b/src/soc/intel/apollolake/nhlt.c
@@ -260,7 +260,7 @@ int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink)
int nhlt_soc_add_rt5682(struct nhlt *nhlt, int hwlink)
{
- /* Virtual bus id of SSP links are the hardware port ids proper. */
- return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5682_descriptors,
- ARRAY_SIZE(rt5682_descriptors));
+ /* Virtual bus id of SSP links are the hardware port ids proper. */
+ return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5682_descriptors,
+ ARRAY_SIZE(rt5682_descriptors));
}
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c
index 5da510486b..451993df2f 100644
--- a/src/soc/intel/baytrail/gpio.c
+++ b/src/soc/intel/baytrail/gpio.c
@@ -170,7 +170,7 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
}
static void setup_gpio_route(const struct soc_gpio_map *sus,
- const struct soc_gpio_map *core)
+ const struct soc_gpio_map *core)
{
uint32_t route_reg = 0;
int i;
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index 30e6d1d94b..51c3ea065b 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -52,7 +52,7 @@ uint16_t get_pmbase(void)
}
static void print_num_status_bits(int num_bits, uint32_t status,
- const char *bit_names[])
+ const char *bit_names[])
{
int i;
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 027e0d8edc..07b801093f 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -97,8 +97,8 @@ static void spi_init(void)
}
/* Entry from cache-as-ram.inc. */
-void *asmlinkage romstage_main(unsigned long bist,
- uint32_t tsc_low, uint32_t tsc_hi)
+void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low,
+ uint32_t tsc_hi)
{
struct romstage_params rp = {
.bist = bist,
diff --git a/src/soc/intel/cannonlake/cbmem.c b/src/soc/intel/cannonlake/cbmem.c
index 0f47173061..300556a45f 100644
--- a/src/soc/intel/cannonlake/cbmem.c
+++ b/src/soc/intel/cannonlake/cbmem.c
@@ -17,6 +17,6 @@
void *cbmem_top(void)
{
- /* not implemented yet */
+ /* not implemented yet */
return (void *) NULL;
}
diff --git a/src/soc/intel/cannonlake/nhlt.c b/src/soc/intel/cannonlake/nhlt.c
index ff1b4464ba..ca31d39574 100644
--- a/src/soc/intel/cannonlake/nhlt.c
+++ b/src/soc/intel/cannonlake/nhlt.c
@@ -231,7 +231,7 @@ static const struct nhlt_endp_descriptor max98373_descriptors[] = {
.did = NHLT_DID_SSP,
.formats = max98373_capture_formats,
.num_formats = ARRAY_SIZE(max98373_capture_formats),
- },
+ },
};
int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels)
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 45ee940849..225914c5b5 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -155,8 +155,8 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count)
if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))
dpr_size = sa_get_dpr_size();
- /* Get SoC reserve memory size as per user selection */
- reserved_mmio_size = soc_reserved_mmio_size();
+ /* Get SoC reserve memory size as per user selection */
+ reserved_mmio_size = soc_reserved_mmio_size();
top_of_ram = (uintptr_t)cbmem_top();
diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c
index 72cf158b21..72ba517d52 100644
--- a/src/soc/intel/fsp_baytrail/gpio.c
+++ b/src/soc/intel/fsp_baytrail/gpio.c
@@ -186,7 +186,7 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
}
static void setup_gpio_route(const struct soc_gpio_map *sus,
- const struct soc_gpio_map *core)
+ const struct soc_gpio_map *core)
{
uint32_t route_reg = 0;
int i;
@@ -319,7 +319,7 @@ void write_ssus_gpio(uint8_t gpio_num, uint8_t val)
* pad value: PAD_VAL_HIGH / PAD_VAL_LOW
*/
static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num,
- uint32_t pconf0, uint32_t pad_val)
+ uint32_t pconf0, uint32_t pad_val)
{
uint32_t reg;
uint32_t *pad_addr;
diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl
index f99b7c3fc7..9798798504 100644
--- a/src/soc/intel/skylake/acpi/dptf/thermal.asl
+++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl
@@ -266,34 +266,34 @@ Device (TSR1)
#ifdef DPTF_ENABLE_FAN_CONTROL
#ifdef DPTF_TSR1_ACTIVE_AC0
- Method (_AC0)
- {
- Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0))
- }
+ Method (_AC0)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0))
+ }
#endif
#ifdef DPTF_TSR1_ACTIVE_AC1
- Method (_AC1)
- {
- Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1))
- }
+ Method (_AC1)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1))
+ }
#endif
#ifdef DPTF_TSR1_ACTIVE_AC2
- Method (_AC2)
- {
- Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2))
- }
+ Method (_AC2)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2))
+ }
#endif
#ifdef DPTF_TSR1_ACTIVE_AC3
- Method (_AC3)
- {
- Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3))
- }
+ Method (_AC3)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3))
+ }
#endif
#ifdef DPTF_TSR1_ACTIVE_AC4
- Method (_AC4)
- {
- Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4))
- }
+ Method (_AC4)
+ {
+ Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4))
+ }
#endif
#endif
}
diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl
index 29367de6dd..a23d78abd9 100644
--- a/src/soc/intel/skylake/acpi/xhci.asl
+++ b/src/soc/intel/skylake/acpi/xhci.asl
@@ -195,8 +195,8 @@ Device (XHCI)
Store (3, ^UPSW)
/* Enable d3hot and SS link trunk clock gating */
- Store(One, ^D3HE)
- Store(One, ^STGE)
+ Store(One, ^D3HE)
+ Store(One, ^STGE)
/* Now put device in D3 */
Store (3, Local0)
diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c
index beb455874f..0e3a4130b1 100644
--- a/src/soc/intel/skylake/nhlt/max98373.c
+++ b/src/soc/intel/skylake/nhlt/max98373.c
@@ -75,7 +75,7 @@ static const struct nhlt_endp_descriptor max98373_descriptors[] = {
.did = NHLT_DID_SSP,
.formats = max98373_capture_formats,
.num_formats = ARRAY_SIZE(max98373_capture_formats),
- },
+ },
};
int nhlt_soc_add_max98373(struct nhlt *nhlt, int hwlink)