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-rw-r--r--src/soc/intel/alderlake/chip.h2
-rw-r--r--src/soc/intel/cannonlake/chip.h2
-rw-r--r--src/soc/intel/elkhartlake/chip.h2
-rw-r--r--src/soc/intel/icelake/chip.h3
-rw-r--r--src/soc/intel/jasperlake/chip.h2
-rw-r--r--src/soc/intel/skylake/chip.h3
-rw-r--r--src/soc/intel/tigerlake/chip.h3
7 files changed, 2 insertions, 15 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index aaf03f510f..428fd4deeb 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -185,8 +185,6 @@ struct soc_intel_alderlake_config {
uint8_t HeciEnabled;
/* PL2 Override value in Watts */
uint32_t tdp_pl2_override;
- /* Intel Speed Shift Technology */
- uint8_t speed_shift_enable;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
uint8_t eist_enable;
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 69a2cf2f48..7f428a21f0 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -261,8 +261,6 @@ struct soc_intel_cannonlake_config {
/* Enables support for Teton Glacier hybrid storage device */
uint8_t TetonGlacierMode;
- /* Intel Speed Shift Technology */
- uint8_t speed_shift_enable;
/* Enable VR specific mailbox command
* 00b - no VR specific cmd sent
* 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index 5037147d74..26d0f0d666 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -149,8 +149,6 @@ struct soc_intel_elkhartlake_config {
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;
- /* Intel Speed Shift Technology */
- uint8_t speed_shift_enable;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
uint8_t eist_enable;
diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h
index 386e77520a..e1b697e3c7 100644
--- a/src/soc/intel/icelake/chip.h
+++ b/src/soc/intel/icelake/chip.h
@@ -169,8 +169,7 @@ struct soc_intel_icelake_config {
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;
- /* Intel Speed Shift Technology */
- uint8_t speed_shift_enable;
+
/* Enable VR specific mailbox command
* 00b - no VR specific cmd sent
* 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 4410de9310..5e9053063b 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -149,8 +149,6 @@ struct soc_intel_jasperlake_config {
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;
- /* Intel Speed Shift Technology */
- uint8_t speed_shift_enable;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
uint8_t eist_enable;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 2584d5d809..41482f10bd 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -461,8 +461,7 @@ struct soc_intel_skylake_config {
*/
u8 HeciEnabled;
u8 PmTimerDisabled;
- /* Intel Speed Shift Technology */
- u8 speed_shift_enable;
+
/*
* Enable VR specific mailbox command
* 000b - Don't Send any VR command
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index fb6cda0919..f752b5f415 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -271,9 +271,6 @@ struct soc_intel_tigerlake_config {
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;
- /* Intel Speed Shift Technology */
- uint8_t speed_shift_enable;
-
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
uint8_t eist_enable;