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-rw-r--r--src/soc/intel/skylake/chip.c3
-rw-r--r--src/soc/intel/skylake/include/soc/pci_devs.h4
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index ef16f388d7..2707353225 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -247,6 +247,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
dev = pcidev_path_on_root(SA_DEVFN_IMGU);
params->SaImguEnable = dev && dev->enabled;
+ dev = pcidev_path_on_root(SA_DEVFN_CHAP);
+ tconfig->ChapDeviceEnable = dev && dev->enabled;
+
dev = pcidev_path_on_root(PCH_DEVFN_CSE_3);
params->Heci3Enabled = dev && dev->enabled;
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index 319a12b53a..661ed5cd65 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -42,6 +42,10 @@
#define SA_DEVFN_IMGU PCI_DEVFN(SA_DEV_SLOT_IMGU, 0)
#define SA_DEV_IMGU PCI_DEV(0, SA_DEV_SLOT_IMGU, 0)
+#define SA_DEV_SLOT_CHAP 0x07
+#define SA_DEVFN_CHAP PCI_DEVFN(SA_DEV_SLOT_CHAP, 0)
+#define SA_DEV_CHAP PCI_DEV(0, SA_DEV_SLOT_CHAP, 0)
+
#define SA_DEV_SLOT_GMM 0x08
#define SA_DEVFN_GMM PCI_DEVFN(SA_DEV_SLOT_GMM, 0)
#define SA_DEV_GMM PCI_DEV(0, SA_DEV_SLOT_GMM, 0)