diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/alderlake/pmutil.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/pmutil.c | 13 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/pmutil.c | 13 | ||||
| -rw-r--r-- | src/soc/intel/icelake/pmutil.c | 13 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/pmutil.c | 13 | ||||
| -rw-r--r-- | src/soc/intel/skylake/pmutil.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/pmutil.c | 13 |
7 files changed, 28 insertions, 47 deletions
diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index 43d5084356..d8308b4019 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -209,10 +209,8 @@ static inline int deep_s3_enabled(void) } /* Return 0, 3, or 5 to indicate the previous sleep state. */ -int soc_prev_sleep_state(const struct chipset_power_state *ps, - int prev_sleep_state) +int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) { - /* * Check for any power failure to determine if this a wake from * S5 because the PCH does not set the WAK_STS bit when waking diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index b2dbfbe6d0..bf4e34fafb 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -202,15 +202,13 @@ static inline int deep_s3_enabled(void) } /* Return 0, 3, or 5 to indicate the previous sleep state. */ -int soc_prev_sleep_state(const struct chipset_power_state *ps, - int prev_sleep_state) +int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) { - /* * Check for any power failure to determine if this a wake from - * S5 because the PCH does not set the WAK_STS bit when waking - * from a true G3 state. - */ + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) prev_sleep_state = ACPI_S5; @@ -241,8 +239,7 @@ void soc_fill_power_state(struct chipset_power_state *ps) ps->tco1_sts = tco_read_reg(TCO1_STS); ps->tco2_sts = tco_read_reg(TCO2_STS); - printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", - ps->tco1_sts, ps->tco2_sts); + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); pmc = pmc_mmio_regs(); ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index b969ba5200..e54da432bd 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -202,15 +202,13 @@ static inline int deep_s3_enabled(void) } /* Return 0, 3, or 5 to indicate the previous sleep state. */ -int soc_prev_sleep_state(const struct chipset_power_state *ps, - int prev_sleep_state) +int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) { - /* * Check for any power failure to determine if this a wake from - * S5 because the PCH does not set the WAK_STS bit when waking - * from a true G3 state. - */ + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) prev_sleep_state = ACPI_S5; @@ -241,8 +239,7 @@ void soc_fill_power_state(struct chipset_power_state *ps) ps->tco1_sts = tco_read_reg(TCO1_STS); ps->tco2_sts = tco_read_reg(TCO2_STS); - printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", - ps->tco1_sts, ps->tco2_sts); + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); pmc = pmc_mmio_regs(); ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 263bfa2e34..9cc6f02df2 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -202,15 +202,13 @@ static inline int deep_s3_enabled(void) } /* Return 0, 3, or 5 to indicate the previous sleep state. */ -int soc_prev_sleep_state(const struct chipset_power_state *ps, - int prev_sleep_state) +int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) { - /* * Check for any power failure to determine if this a wake from - * S5 because the PCH does not set the WAK_STS bit when waking - * from a true G3 state. - */ + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) prev_sleep_state = ACPI_S5; @@ -241,8 +239,7 @@ void soc_fill_power_state(struct chipset_power_state *ps) ps->tco1_sts = tco_read_reg(TCO1_STS); ps->tco2_sts = tco_read_reg(TCO2_STS); - printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", - ps->tco1_sts, ps->tco2_sts); + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); pmc = pmc_mmio_regs(); ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index 7a42d771ae..3b93d32940 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -202,15 +202,13 @@ static inline int deep_s3_enabled(void) } /* Return 0, 3, or 5 to indicate the previous sleep state. */ -int soc_prev_sleep_state(const struct chipset_power_state *ps, - int prev_sleep_state) +int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) { - /* * Check for any power failure to determine if this a wake from - * S5 because the PCH does not set the WAK_STS bit when waking - * from a true G3 state. - */ + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) prev_sleep_state = ACPI_S5; @@ -241,8 +239,7 @@ void soc_fill_power_state(struct chipset_power_state *ps) ps->tco1_sts = tco_read_reg(TCO1_STS); ps->tco2_sts = tco_read_reg(TCO2_STS); - printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", - ps->tco1_sts, ps->tco2_sts); + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); pmc = pmc_mmio_regs(); ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 6d16f52695..906a1cf56f 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -204,8 +204,7 @@ int vbnv_cmos_failed(void) } /* Return 0, 3, or 5 to indicate the previous sleep state. */ -int soc_prev_sleep_state(const struct chipset_power_state *ps, - int prev_sleep_state) +int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) { /* * Check for any power failure to determine if this a wake from @@ -242,8 +241,7 @@ void soc_fill_power_state(struct chipset_power_state *ps) ps->tco1_sts = tco_read_reg(TCO1_STS); ps->tco2_sts = tco_read_reg(TCO2_STS); - printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", - ps->tco1_sts, ps->tco2_sts); + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A); ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B); diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 39fc36b46d..c980a2cbbd 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -208,15 +208,13 @@ static inline int deep_s3_enabled(void) } /* Return 0, 3, or 5 to indicate the previous sleep state. */ -int soc_prev_sleep_state(const struct chipset_power_state *ps, - int prev_sleep_state) +int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state) { - /* * Check for any power failure to determine if this a wake from - * S5 because the PCH does not set the WAK_STS bit when waking - * from a true G3 state. - */ + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) prev_sleep_state = ACPI_S5; @@ -247,8 +245,7 @@ void soc_fill_power_state(struct chipset_power_state *ps) ps->tco1_sts = tco_read_reg(TCO1_STS); ps->tco2_sts = tco_read_reg(TCO2_STS); - printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", - ps->tco1_sts, ps->tco2_sts); + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); pmc = pmc_mmio_regs(); ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); |