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-rw-r--r--src/soc/intel/cannonlake/bootblock/pch.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index cca70c21ad..47eaceb3f9 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -16,6 +16,7 @@
#include <device/device.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/gspi.h>
#include <intelblocks/pcr.h>
#include <intelblocks/rtc.h>
#include <intelblocks/pmclib.h>
@@ -98,6 +99,7 @@ static void soc_config_pwrmbase(void)
void bootblock_pch_early_init(void)
{
fast_spi_early_init(SPI_BASE_ADDRESS);
+ gspi_early_bar_init();
enable_p2sbbar();
/*
* Enabling PWRM Base for accessing