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-rw-r--r--src/soc/intel/baytrail/Kconfig2
-rw-r--r--src/soc/intel/baytrail/Makefile.inc2
-rw-r--r--src/soc/intel/baytrail/include/soc/reset.h32
-rw-r--r--src/soc/intel/baytrail/reset.c43
-rw-r--r--src/soc/intel/baytrail/romstage/raminit.c12
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c1
-rw-r--r--src/soc/intel/broadwell/Kconfig2
-rw-r--r--src/soc/intel/broadwell/Makefile.inc2
-rw-r--r--src/soc/intel/broadwell/include/soc/reset.h21
-rw-r--r--src/soc/intel/broadwell/reset.c45
-rw-r--r--src/soc/intel/broadwell/romstage/raminit.c6
-rw-r--r--src/soc/intel/broadwell/romstage/romstage.c1
-rw-r--r--src/soc/intel/fsp_baytrail/Kconfig2
-rw-r--r--src/soc/intel/fsp_baytrail/Makefile.inc2
-rw-r--r--src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c6
-rw-r--r--src/soc/intel/fsp_baytrail/include/soc/reset.h32
-rw-r--r--src/soc/intel/fsp_baytrail/reset.c43
-rw-r--r--src/soc/intel/fsp_broadwell_de/Kconfig2
-rw-r--r--src/soc/intel/fsp_broadwell_de/Makefile.inc2
-rw-r--r--src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c4
-rw-r--r--src/soc/intel/fsp_broadwell_de/include/soc/reset.h24
-rw-r--r--src/soc/intel/fsp_broadwell_de/reset.c29
22 files changed, 15 insertions, 300 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 7b877668cc..66fcded42d 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -17,7 +17,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
select SUPPORT_CPU_UCODE_IN_CBFS
select HAVE_SMI_HANDLER
- select HAVE_HARD_RESET
+ select SOUTHBRIDGE_INTEL_COMMON_RESET
select NO_FIXED_XIP_ROM_SIZE
select PARALLEL_MP
select PCIEXP_ASPM
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index ba9517d5dc..324dcdd715 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -23,8 +23,6 @@ smm-y += iosf.c
ramstage-y += northcluster.c
ramstage-y += ramstage.c
ramstage-y += gpio.c
-romstage-y += reset.c
-ramstage-y += reset.c
ramstage-y += cpu.c
romstage-y += pmutil.c
ramstage-y += pmutil.c
diff --git a/src/soc/intel/baytrail/include/soc/reset.h b/src/soc/intel/baytrail/include/soc/reset.h
deleted file mode 100644
index 4a36207623..0000000000
--- a/src/soc/intel/baytrail/include/soc/reset.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _BAYTRAIL_RESET_H_
-#define _BAYTRAIL_RESET_H_
-#include <reset.h>
-
-/* Bay Trail has the following types of resets:
- * - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92
- * - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9
- * - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9
- * - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9
- * - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but
- * with ETR[20] set.
- */
-
-void cold_reset(void);
-void warm_reset(void);
-
-#endif /* _BAYTRAIL_RESET_H_ */
diff --git a/src/soc/intel/baytrail/reset.c b/src/soc/intel/baytrail/reset.c
deleted file mode 100644
index e38a2e6ec8..0000000000
--- a/src/soc/intel/baytrail/reset.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <soc/pmc.h>
-#include <soc/reset.h>
-
-void cold_reset(void)
-{
- /* S0->S5->S0 trip. */
- outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
-}
-
-void warm_reset(void)
-{
- /* PMC_PLTRST# asserted. */
- outb(RST_CPU | SYS_RST, RST_CNT);
-}
-
-void do_soft_reset(void)
-{
- /* Sends INIT# to CPU */
- outb(RST_CPU, RST_CNT);
-}
-
-void do_hard_reset(void)
-{
- /* Don't power cycle on hard_reset(). It's not really clear what the
- * semantics should be for the meaning of hard_reset(). */
- warm_reset();
-}
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 45bc75b9b3..cc055c0dbe 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -18,6 +18,7 @@
#include <assert.h>
#include <cbfs.h>
#include <cbmem.h>
+#include <cf9_reset.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <halt.h>
@@ -26,18 +27,11 @@
#include <soc/iomap.h>
#include <soc/iosf.h>
#include <soc/pci_devs.h>
-#include <soc/reset.h>
#include <soc/romstage.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <security/vboot/vboot_common.h>
-static void reset_system(void)
-{
- warm_reset();
- halt();
-}
-
static void enable_smbus(void)
{
uint32_t reg;
@@ -134,7 +128,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
/* If waking from S3 and no cache then. */
printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
- reset_system();
+ system_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
}
@@ -165,7 +159,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
- reset_system();
+ system_reset();
#endif
}
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 07b801093f..af67434a92 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -36,7 +36,6 @@
#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <soc/pmc.h>
-#include <soc/reset.h>
#include <soc/romstage.h>
#include <soc/smm.h>
#include <soc/spi.h>
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index ffd7c7311f..066f1bed48 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -20,7 +20,7 @@ config CPU_SPECIFIC_OPTIONS
select SUPPORT_CPU_UCODE_IN_CBFS
select HAVE_MONOTONIC_TIMER
select HAVE_SMI_HANDLER
- select HAVE_HARD_RESET
+ select SOUTHBRIDGE_INTEL_COMMON_RESET
select HAVE_USBDEBUG
select IOAPIC
select REG_SCRIPT
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index c4f45388f8..4e4d3ebe55 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -43,8 +43,6 @@ romstage-y += pmutil.c
smm-y += pmutil.c
ramstage-y += ramstage.c
ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
-ramstage-y += reset.c
-romstage-y += reset.c
ramstage-y += sata.c
ramstage-y += serialio.c
ramstage-y += smbus.c
diff --git a/src/soc/intel/broadwell/include/soc/reset.h b/src/soc/intel/broadwell/include/soc/reset.h
deleted file mode 100644
index 4edb598ae2..0000000000
--- a/src/soc/intel/broadwell/include/soc/reset.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _BROADWELL_RESET_H_
-#define _BROADWELL_RESET_H_
-
-void reset_system(void);
-
-#endif
diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c
deleted file mode 100644
index ad90dcd880..0000000000
--- a/src/soc/intel/broadwell/reset.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <halt.h>
-#include <reset.h>
-#include <soc/reset.h>
-
-/*
- * Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92
- * Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9
- * Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9
- * Warm reset (PLTRST# assertion) - write 0x6 to I/O 0xcf9
- * Global reset (S0->S5->S0 with ME reset) - write 0x6 or 0xe to 0xcf9 but
- * with ETR[20] set.
- */
-
-void do_soft_reset(void)
-{
- outb(0x04, 0xcf9);
-}
-
-void do_hard_reset(void)
-{
- outb(0x06, 0xcf9);
-}
-
-void reset_system(void)
-{
- hard_reset();
- halt();
-}
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 54db3d1564..c4a3b2c9d9 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -18,6 +18,7 @@
#include <assert.h>
#include <cbfs.h>
#include <cbmem.h>
+#include <cf9_reset.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <lib.h>
@@ -33,7 +34,6 @@
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/pm.h>
-#include <soc/reset.h>
#include <soc/romstage.h>
#include <soc/smm.h>
#include <soc/systemagent.h>
@@ -63,7 +63,7 @@ void raminit(struct pei_data *pei_data)
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
- reset_system();
+ system_reset();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
}
@@ -108,7 +108,7 @@ void raminit(struct pei_data *pei_data)
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
- reset_system();
+ system_reset();
#endif
}
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index a6691ab9f9..3abc853975 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -32,7 +32,6 @@
#include <soc/me.h>
#include <soc/pei_data.h>
#include <soc/pm.h>
-#include <soc/reset.h>
#include <soc/romstage.h>
#include <soc/spi.h>
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index 2019b6d9a1..7d82f3f49d 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -29,7 +29,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select HAVE_SMI_HANDLER
- select HAVE_HARD_RESET
+ select SOUTHBRIDGE_INTEL_COMMON_RESET
select NO_RELOCATABLE_RAMSTAGE
select PARALLEL_MP
select REG_SCRIPT
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 0cf99dea4c..d8c4f71c32 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -45,8 +45,6 @@ romstage-y += gpio.c
romstage-y += pmutil.c
ramstage-y += pmutil.c
ramstage-y += southcluster.c
-romstage-y += reset.c
-ramstage-y += reset.c
ramstage-y += cpu.c
ramstage-y += acpi.c
ramstage-y += lpe.c
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index a7268aa20b..c5863f459f 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -19,13 +19,13 @@
#include <console/console.h>
#include <bootstate.h>
#include <cbmem.h>
+#include <cf9_reset.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <soc/pci_devs.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include "../chip.h"
#include <arch/io.h>
-#include <soc/reset.h>
#include <soc/pmc.h>
#include <soc/acpi.h>
#include <soc/iomap.h>
@@ -323,7 +323,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
/* Reboot */
printk(BIOS_WARNING,"Rebooting..\n" );
- warm_reset();
+ system_reset();
/* Should not reach here.. */
die("Reboot System\n");
}
@@ -343,7 +343,7 @@ void ChipsetFspReturnPoint(EFI_STATUS Status,
*(void **)CBMEM_FSP_HOB_PTR=HobListPtr;
if (Status == 0xFFFFFFFF) {
- warm_reset();
+ system_reset();
}
romstage_main_continue(Status, HobListPtr);
}
diff --git a/src/soc/intel/fsp_baytrail/include/soc/reset.h b/src/soc/intel/fsp_baytrail/include/soc/reset.h
deleted file mode 100644
index 4a36207623..0000000000
--- a/src/soc/intel/fsp_baytrail/include/soc/reset.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _BAYTRAIL_RESET_H_
-#define _BAYTRAIL_RESET_H_
-#include <reset.h>
-
-/* Bay Trail has the following types of resets:
- * - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92
- * - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9
- * - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9
- * - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9
- * - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but
- * with ETR[20] set.
- */
-
-void cold_reset(void);
-void warm_reset(void);
-
-#endif /* _BAYTRAIL_RESET_H_ */
diff --git a/src/soc/intel/fsp_baytrail/reset.c b/src/soc/intel/fsp_baytrail/reset.c
deleted file mode 100644
index e38a2e6ec8..0000000000
--- a/src/soc/intel/fsp_baytrail/reset.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <soc/pmc.h>
-#include <soc/reset.h>
-
-void cold_reset(void)
-{
- /* S0->S5->S0 trip. */
- outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
-}
-
-void warm_reset(void)
-{
- /* PMC_PLTRST# asserted. */
- outb(RST_CPU | SYS_RST, RST_CNT);
-}
-
-void do_soft_reset(void)
-{
- /* Sends INIT# to CPU */
- outb(RST_CPU, RST_CNT);
-}
-
-void do_hard_reset(void)
-{
- /* Don't power cycle on hard_reset(). It's not really clear what the
- * semantics should be for the meaning of hard_reset(). */
- warm_reset();
-}
diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig
index 26c40947a7..ec010b3882 100644
--- a/src/soc/intel/fsp_broadwell_de/Kconfig
+++ b/src/soc/intel/fsp_broadwell_de/Kconfig
@@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
- select HAVE_HARD_RESET
+ select SOUTHBRIDGE_INTEL_COMMON_RESET
select NO_RELOCATABLE_RAMSTAGE
select PARALLEL_MP
select SMP
diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc
index 931266314c..544819088d 100644
--- a/src/soc/intel/fsp_broadwell_de/Makefile.inc
+++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc
@@ -23,8 +23,6 @@ ramstage-y += tsc_freq.c
romstage-y += memmap.c
ramstage-y += memmap.c
ramstage-y += southcluster.c
-romstage-y += reset.c
-ramstage-y += reset.c
ramstage-y += acpi.c
ramstage-y += smbus_common.c
ramstage-y += smbus.c
diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
index 148ffdc367..800f68653b 100644
--- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
@@ -20,11 +20,11 @@
#include <bootstate.h>
#include <cbfs.h>
#include <cbmem.h>
+#include <cf9_reset.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <soc/pci_devs.h>
-#include <soc/reset.h>
#include <soc/romstage.h>
#include <chip.h>
#include <fsp.h>
@@ -142,7 +142,7 @@ void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr)
*(void **)CBMEM_FSP_HOB_PTR = HobListPtr;
if (Status == 0xFFFFFFFF) {
- warm_reset();
+ system_reset();
}
romstage_main_continue(Status, HobListPtr);
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/reset.h b/src/soc/intel/fsp_broadwell_de/include/soc/reset.h
deleted file mode 100644
index fa0ceac091..0000000000
--- a/src/soc/intel/fsp_broadwell_de/include/soc/reset.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_RESET_H_
-#define _SOC_RESET_H_
-
-#include <reset.h>
-
-void warm_reset(void);
-
-#endif /* _SOC_RESET_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/reset.c b/src/soc/intel/fsp_broadwell_de/reset.c
deleted file mode 100644
index 78d74939e3..0000000000
--- a/src/soc/intel/fsp_broadwell_de/reset.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <soc/reset.h>
-
-void warm_reset(void)
-{
- outb(0x00, 0xcf9);
- outb(0x06, 0xcf9);
-}
-
-void do_hard_reset(void)
-{
- warm_reset();
-}