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-rw-r--r--src/soc/intel/baytrail/acpi/pcie.asl109
-rw-r--r--src/soc/intel/baytrail/acpi/southcluster.asl3
2 files changed, 112 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/acpi/pcie.asl b/src/soc/intel/baytrail/acpi/pcie.asl
new file mode 100644
index 0000000000..5ad4e788fc
--- /dev/null
+++ b/src/soc/intel/baytrail/acpi/pcie.asl
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Intel SOC PCIe support */
+
+Device (RP01)
+{
+ Name (_ADR, 0x001c0000)
+
+ Method (_PRT)
+ {
+ If (PICM) {
+ Return (Package() {
+ #undef PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
+ })
+ } Else {
+ Return (Package() {
+ #define PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
+ })
+ }
+ }
+}
+
+Device (RP02)
+{
+ Name (_ADR, 0x001c0001)
+
+ Method (_PRT)
+ {
+ If (PICM) {
+ Return (Package() {
+ #undef PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
+ })
+ } Else {
+ Return (Package() {
+ #define PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
+ })
+ }
+ }
+}
+
+Device (RP03)
+{
+ Name (_ADR, 0x001c0002)
+
+ Method (_PRT)
+ {
+ If (PICM) {
+ Return (Package() {
+ #undef PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
+ })
+ } Else {
+ Return (Package() {
+ #define PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
+ })
+ }
+ }
+}
+
+Device (RP04)
+{
+ Name (_ADR, 0x001c0003)
+
+ Method (_PRT)
+ {
+ If (PICM) {
+ Return (Package() {
+ #undef PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
+ })
+ } Else {
+ Return (Package() {
+ #define PIC_MODE
+ #include <soc/intel/baytrail/acpi/irq_helper.h>
+ PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
+ })
+ }
+ }
+}
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 5382182659..354515ba67 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -254,6 +254,9 @@ Device (IOSF)
// IRQ routing for each PCI device
#include "irqroute.asl"
+// PCI Express Ports 0:1c.x
+#include "pcie.asl"
+
Scope (\_SB)
{
// GPIO Devices