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-rw-r--r--src/soc/intel/cannonlake/Kconfig2
-rw-r--r--src/soc/intel/cannonlake/elog.c17
2 files changed, 17 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 37e42f30e2..d697620725 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -95,6 +95,8 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_SA
+ select SOC_INTEL_COMMON_BLOCK_XHCI
+ select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_PCH_BASE
diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c
index 2ec6b410df..141aa45b02 100644
--- a/src/soc/intel/cannonlake/elog.c
+++ b/src/soc/intel/cannonlake/elog.c
@@ -20,9 +20,22 @@
#include <stdint.h>
#include <elog.h>
#include <intelblocks/pmclib.h>
+#include <intelblocks/xhci.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
+#define XHCI_USB2_PORT_STATUS_REG 0x480
+#define XHCI_USB3_PORT_STATUS_REG 0x580
+#define XHCI_USB2_PORT_NUM 14
+#define XHCI_USB3_PORT_NUM 10
+
+static const struct xhci_usb_info usb_info = {
+ .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG,
+ .num_usb2_ports = XHCI_USB2_PORT_NUM,
+ .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG,
+ .num_usb3_ports = XHCI_USB3_PORT_NUM,
+};
+
static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
{
int i;
@@ -53,9 +66,9 @@ static void pch_log_wake_source(struct chipset_power_state *ps)
if (ps->gpe0_sts[GPE_STD] & PME_STS)
elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
- /* Internal PME (TODO: determine wake device) */
+ /* XHCI - "Power Management Event Bus 0" events include XHCI */
if (ps->gpe0_sts[GPE_STD] & PME_B0_STS)
- elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
+ pch_xhci_update_wake_event(&usb_info);
/* SMBUS Wake */
if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)