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-rw-r--r--src/soc/intel/cannonlake/chip.h3
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c1
2 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 9c7c17147e..451c920fae 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -387,9 +387,6 @@ struct soc_intel_cannonlake_config {
uint8_t SlowSlewRateForSa;
uint8_t SlowSlewRateForFivr;
- /* DMI Power Optimizer */
- uint8_t dmipwroptimize;
-
/* SATA Power Optimizer */
uint8_t satapwroptimize;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index f48a626be9..76d40aa624 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -377,7 +377,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr;
/* Power Optimizer */
- params->PchPwrOptEnable = config->dmipwroptimize;
params->SataPwrOptEnable = config->satapwroptimize;
/* Disable PCH ACPI timer */