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-rw-r--r--src/soc/intel/xeon_sp/cpx/hob_display.c16
-rw-r--r--src/soc/intel/xeon_sp/cpx/romstage.c4
2 files changed, 8 insertions, 12 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/hob_display.c b/src/soc/intel/xeon_sp/cpx/hob_display.c
index 37c0c7e773..d10a0f6515 100644
--- a/src/soc/intel/xeon_sp/cpx/hob_display.c
+++ b/src/soc/intel/xeon_sp/cpx/hob_display.c
@@ -97,14 +97,14 @@ void soc_display_iio_universal_data_hob(void)
printk(BIOS_DEBUG, "\t===================== PLATFORM DATA =====================\n");
printk(BIOS_DEBUG, "\tPlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase);
printk(BIOS_DEBUG, "\tPlatGlobalIoLimit: 0x%x\n", hob->PlatformData.PlatGlobalIoLimit);
- printk(BIOS_DEBUG, "\tPlatGlobalMmiolBase: 0x%x\n",
- hob->PlatformData.PlatGlobalMmiolBase);
- printk(BIOS_DEBUG, "\tPlatGlobalMmiolLimit: 0x%x\n",
- hob->PlatformData.PlatGlobalMmiolLimit);
- printk(BIOS_DEBUG, "\tPlatGlobalMmiohBase: 0x%llx\n",
- hob->PlatformData.PlatGlobalMmiohBase);
- printk(BIOS_DEBUG, "\tPlatGlobalMmiohLimit: 0x%llx\n",
- hob->PlatformData.PlatGlobalMmiohLimit);
+ printk(BIOS_DEBUG, "\tPlatGlobalMmio32Base: 0x%x\n",
+ hob->PlatformData.PlatGlobalMmio32Base);
+ printk(BIOS_DEBUG, "\tPlatGlobalMmio32Limit: 0x%x\n",
+ hob->PlatformData.PlatGlobalMmio32Limit);
+ printk(BIOS_DEBUG, "\tPlatGlobalMmio64Base: 0x%llx\n",
+ hob->PlatformData.PlatGlobalMmio64Base);
+ printk(BIOS_DEBUG, "\tPlatGlobalMmio64Limit: 0x%llx\n",
+ hob->PlatformData.PlatGlobalMmio64Limit);
printk(BIOS_DEBUG, "\tMemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize);
printk(BIOS_DEBUG, "\tMemIedSize: 0x%x\n", hob->PlatformData.MemIedSize);
printk(BIOS_DEBUG, "\tPciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase);
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c
index cbaa006219..4b97ddc96d 100644
--- a/src/soc/intel/xeon_sp/cpx/romstage.c
+++ b/src/soc/intel/xeon_sp/cpx/romstage.c
@@ -33,7 +33,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
/* Bitmask for valid sockets supported by the board */
m_cfg->BoardTypeBitmask = 0x11111111;
- m_cfg->mmiolSize = 0x0;
m_cfg->mmiohBase = 0x2000;
/* default: 0x1 (enable), set to 0x2 (auto) */
@@ -65,9 +64,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
/* the wait time in units of 1000us for PBSP to check in */
m_cfg->WaitTimeForPSBP = 0x7530;
- m_cfg->OemHookPostTopologyDiscovery = 0xFFF7727B;
- m_cfg->OemGetResourceMapUpdate = 0xFFF7727C;
-
/* Needed to avoid FSP-M reset. The default value of 0x01 is for MinPlatform */
m_cfg->PchAdrEn = 0x02;