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-rw-r--r--src/soc/intel/cannonlake/Kconfig1
-rw-r--r--src/soc/intel/cannonlake/chip.h2
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c5
-rw-r--r--src/soc/intel/skylake/Kconfig1
-rw-r--r--src/soc/intel/skylake/chip.c3
-rw-r--r--src/soc/intel/skylake/chip.h1
6 files changed, 6 insertions, 7 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index d61435aaa6..7b9b88be61 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -97,6 +97,7 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0
select REG_SCRIPT
+ select PM_ACPI_TIMER_OPTIONAL
select PMC_GLOBAL_RESET_ENABLE_LOCK
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index dc24e9bd8f..2a52627be7 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -273,8 +273,6 @@ struct soc_intel_cannonlake_config {
/* Enable C6 DRAM */
uint8_t enable_c6dram;
- uint8_t PmTimerDisabled;
-
/*
* SLP_S3 Minimum Assertion Width Policy
* 1 = 60us
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index fe7641f27b..9b28d3d795 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -248,6 +248,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
+ params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);
+
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
@@ -432,9 +434,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa;
params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr;
- /* Disable PCH ACPI timer */
- params->EnableTcoTimer = !config->PmTimerDisabled;
-
/* Apply minimum assertion width settings if non-zero */
if (config->PchPmSlpS3MinAssert)
params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index f71beaed52..ce46d06b03 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
select PLATFORM_USES_FSP2_0
select REG_SCRIPT
select SA_ENABLE_DPR
+ select PM_ACPI_TIMER_OPTIONAL
select PMC_GLOBAL_RESET_ENABLE_LOCK
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 1e13428252..e2aee07114 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -235,6 +235,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Legacy 8254 timer support */
params->Early8254ClockGatingEnable = !CONFIG(USE_LEGACY_8254_TIMER);
+ params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);
+
memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
sizeof(params->SerialIoDevMode));
@@ -297,7 +299,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Device4Enable = dev && dev->enabled;
dev = pcidev_path_on_root(PCH_DEVFN_THERMAL);
params->PchThermalDeviceEnable = dev && dev->enabled;
- params->EnableTcoTimer = !config->PmTimerDisabled;
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 41482f10bd..0bab45ab22 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -460,7 +460,6 @@ struct soc_intel_skylake_config {
* Setting to 0 (default) disables Heci1 and hides the device from OS
*/
u8 HeciEnabled;
- u8 PmTimerDisabled;
/*
* Enable VR specific mailbox command