3 files changed, 32 insertions, 89 deletions

diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index a0d816ef43..6ec4d389e5 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -15,77 +15,15 @@
  * GNU General Public License for more details.
  */
 
+#include <bootstate.h>
 #include <chip.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include <arch/acpi.h>
-#include <cpu/cpu.h>
-#include <intelblocks/pcr.h>
+#include <intelblocks/pmc.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
-#include <pc80/mc146818rtc.h>
-#include <string.h>
-#include <soc/gpio.h>
-#include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
-#include <cpu/x86/smm.h>
-#include <soc/pcr_ids.h>
-#include <soc/ramstage.h>
-#include <security/vboot/vbnv.h>
-#include <security/vboot/vbnv_layout.h>
-
-static void pch_pmc_add_mmio_resources(device_t dev)
-{
-	struct resource *res;
-
-	/* Memory-mmapped I/O registers. */
-	res = new_resource(dev, PWRMBASE);
-	res->base = PCH_PWRM_BASE_ADDRESS;
-	res->size = PCH_PWRM_BASE_SIZE;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
-			IORESOURCE_FIXED | IORESOURCE_RESERVE;
-}
-
-static void pch_pmc_add_io_resource(device_t dev, u16 base, u16 size, int index)
-{
-	struct resource *res;
-	res = new_resource(dev, index);
-	res->base = base;
-	res->size = size;
-	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static void pch_pmc_add_io_resources(device_t dev)
-{
-	/* PMBASE */
-	pch_pmc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);
-}
-
-static void pch_pmc_read_resources(device_t dev)
-{
-	/* Get the normal PCI resources of this device. */
-	pci_dev_read_resources(dev);
-
-	/* Add non-standard MMIO resources. */
-	pch_pmc_add_mmio_resources(dev);
-
-	/* Add IO resources. */
-	pch_pmc_add_io_resources(dev);
-}
-
-static void pch_set_acpi_mode(void)
-{
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
-		printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
-		outb(APM_CNT_ACPI_DISABLE, APM_CNT);
-		printk(BIOS_DEBUG, "done.\n");
-	}
-}
 
 static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
 {
@@ -128,8 +66,9 @@ static void config_deep_sx(uint32_t deepsx_config)
 	write32(pmcbase + DSX_CFG, reg);
 }
 
-static void pmc_init(struct device *dev)
+static void pmc_init(void *unused)
 {
+	device_t dev = PCH_DEV_PMC;
 	config_t *config = dev->chip_info;
 
 	rtc_init();
@@ -137,28 +76,18 @@ static void pmc_init(struct device *dev)
 	/* Initialize power management */
 	pmc_gpe_init();
 
-	pch_set_acpi_mode();
+	pmc_set_acpi_mode();
 
 	config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
 	config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
 	config_deep_sx(config->deep_sx_config);
 }
 
-static struct device_operations device_ops = {
-	.read_resources		= &pch_pmc_read_resources,
-	.set_resources		= &pci_dev_set_resources,
-	.enable_resources	= &pci_dev_enable_resources,
-	.init			= &pmc_init,
-	.scan_bus		= &scan_lpc_bus,
-};
-
-static const unsigned short pci_device_ids[] = {
-	PCI_DEVICE_ID_INTEL_CNL_PMC,
-	0
-};
-
-static const struct pci_driver pch_lpc __pci_driver = {
-	.ops	 = &device_ops,
-	.vendor	 = PCI_VENDOR_ID_INTEL,
-	.devices = pci_device_ids,
-};
+/*
+* Initialize PMC controller.
+*
+* PMC controller gets hidden from PCI bus during FSP-Silicon init call.
+* Hence PCI enumeration can't be used to initialize bus device and
+* allocate resources.
+*/
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL);
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index b3fad88dd0..a5d18330df 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -128,13 +128,15 @@ const char *const *soc_std_gpe_sts_array(size_t *a)
 	return gpe_sts_bits;
 }
 
+/*
+ * PMC controller gets hidden from PCI bus
+ * during FSP-Silicon init call. Hence PWRMBASE
+ * can't be accessible using PCI configuration space
+ * read/write.
+ */
 uint8_t *pmc_mmio_regs(void)
 {
-	uint32_t reg32;
-
-	reg32 = pci_read_config32(PCH_DEV_PMC, PWRMBASE);
-
-	return (void *)(uintptr_t)ALIGN_DOWN(reg32, 4 * KiB);
+	return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
 }
 
 uint16_t smbus_tco_regs(void)
diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c
index 7ce152dc21..344517d9e8 100644
--- a/src/soc/intel/cannonlake/systemagent.c
+++ b/src/soc/intel/cannonlake/systemagent.c
@@ -17,6 +17,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <device/pci.h>
 #include <intelblocks/systemagent.h>
 #include <soc/iomap.h>
 #include <soc/systemagent.h>
@@ -37,6 +38,17 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
 		{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
 		{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
 		{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
+		/*
+		 * PMC pci device gets hidden from PCI bus due to Silicon
+		 * policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with
+		 * SA resources to ensure that PMCBAR falls under PCI reserved
+		 * memory range.
+		 *
+		 * Note: Don't add any more resource with same offset 0x10
+		 * under this device space.
+		 */
+		{ PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE,
+				"PMCBAR" },
 	};
 
 	sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,