diff options
Diffstat (limited to 'src/soc/intel')
-rw-r--r-- | src/soc/intel/apollolake/spi.c | 22 | ||||
-rw-r--r-- | src/soc/intel/baytrail/spi.c | 2 | ||||
-rw-r--r-- | src/soc/intel/braswell/spi.c | 2 | ||||
-rw-r--r-- | src/soc/intel/common/nvm.c | 7 | ||||
-rw-r--r-- | src/soc/intel/fsp_baytrail/nvm.c | 4 | ||||
-rw-r--r-- | src/soc/intel/fsp_baytrail/spi.c | 2 | ||||
-rw-r--r-- | src/soc/intel/skylake/flash_controller.c | 23 | ||||
-rw-r--r-- | src/soc/intel/skylake/include/soc/flash_controller.h | 13 | ||||
-rw-r--r-- | src/soc/intel/skylake/romstage/spi.c | 1 |
9 files changed, 40 insertions, 36 deletions
diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index d60176a9aa..018572cfab 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -19,12 +19,14 @@ #include <arch/early_variables.h> #include <arch/io.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <soc/intel/common/spi.h> #include <soc/pci_devs.h> #include <soc/spi.h> #include <spi_flash.h> +#include <spi-generic.h> #include <stdlib.h> #include <string.h> @@ -224,7 +226,8 @@ void spi_release_bus(struct spi_slave *slave) /* No magic needed here. */ } -static int nuclear_spi_erase(struct spi_flash *flash, uint32_t offset, size_t len) +static int nuclear_spi_erase(const struct spi_flash *flash, uint32_t offset, + size_t len) { int ret; size_t erase_size; @@ -274,7 +277,8 @@ static size_t get_xfer_len(uint32_t addr, size_t len) return xfer_len; } -static int nuclear_spi_read(struct spi_flash *flash, uint32_t addr, size_t len, void *buf) +static int nuclear_spi_read(const struct spi_flash *flash, uint32_t addr, + size_t len, void *buf) { int ret; size_t xfer_len; @@ -300,8 +304,8 @@ static int nuclear_spi_read(struct spi_flash *flash, uint32_t addr, size_t len, return SUCCESS; } -static int nuclear_spi_write(struct spi_flash *flash, - uint32_t addr, size_t len, const void *buf) +static int nuclear_spi_write(const struct spi_flash *flash, uint32_t addr, + size_t len, const void *buf) { int ret; size_t xfer_len; @@ -326,7 +330,7 @@ static int nuclear_spi_write(struct spi_flash *flash, return SUCCESS; } -static int nuclear_spi_status(struct spi_flash *flash, uint8_t *reg) +static int nuclear_spi_status(const struct spi_flash *flash, uint8_t *reg) { int ret; BOILERPLATE_CREATE_CTX(ctx); @@ -379,10 +383,10 @@ static struct spi_flash *nuclear_flash_probe(struct spi_slave *spi) * flash->status_cmd = ??? */ - flash->write = nuclear_spi_write; - flash->erase = nuclear_spi_erase; - flash->read = nuclear_spi_read; - flash->status = nuclear_spi_status; + flash->internal_write = nuclear_spi_write; + flash->internal_erase = nuclear_spi_erase; + flash->internal_read = nuclear_spi_read; + flash->internal_status = nuclear_spi_status; return flash; } diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index ffe619866f..d651350cd5 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -21,7 +21,7 @@ #include <arch/io.h> #include <console/console.h> #include <device/pci_ids.h> -#include <spi_flash.h> +#include <spi-generic.h> #include <soc/lpc.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 01fe773dea..97ca2e56ef 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -22,7 +22,7 @@ #include <rules.h> #include <soc/lpc.h> #include <soc/pci_devs.h> -#include <spi_flash.h> +#include <spi-generic.h> #include <stdint.h> #include <stdlib.h> #include <string.h> diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index 6b86faf2e8..e44fb940b7 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -81,7 +81,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - return flash->erase(flash, nvm_mmio_to_flash_offset(start), size); + return spi_flash_erase(flash, nvm_mmio_to_flash_offset(start), size); } /* Write data to NVM. Returns 0 on success < 0 on error. */ @@ -89,7 +89,8 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - return flash->write(flash, nvm_mmio_to_flash_offset(start), size, data); + return spi_flash_write(flash, nvm_mmio_to_flash_offset(start), size, + data); } /* Read flash status register to determine if write protect is active */ @@ -107,7 +108,7 @@ int nvm_is_write_protected(void) wp_gpio = get_write_protect_state(); /* Read Status Register 1 */ - if (flash->status(flash, &sr1) < 0) { + if (spi_flash_status(flash, &sr1) < 0) { printk(BIOS_ERR, "Failed to read SPI status register 1\n"); return -1; diff --git a/src/soc/intel/fsp_baytrail/nvm.c b/src/soc/intel/fsp_baytrail/nvm.c index ed0d12165b..6f2fdbbd6a 100644 --- a/src/soc/intel/fsp_baytrail/nvm.c +++ b/src/soc/intel/fsp_baytrail/nvm.c @@ -67,7 +67,7 @@ int nvm_erase(void *start, size_t size) { if (nvm_init() < 0) return -1; - flash->erase(flash, to_flash_offset(start), size); + spi_flash_erase(flash, to_flash_offset(start), size); return 0; } @@ -76,6 +76,6 @@ int nvm_write(void *start, const void *data, size_t size) { if (nvm_init() < 0) return -1; - flash->write(flash, to_flash_offset(start), size, data); + spi_flash_write(flash, to_flash_offset(start), size, data); return 0; } diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 374e7f6a44..b021175961 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include <console/console.h> #include <device/pci_ids.h> -#include <spi_flash.h> +#include <spi-generic.h> #include <soc/lpc.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index 56c7c69527..5a715a4011 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -18,12 +18,12 @@ #include <stdlib.h> #include <string.h> #include <bootstate.h> -#include <spi_flash.h> #include <timer.h> #include <soc/flash_controller.h> #include <soc/intel/common/spi.h> #include <soc/pci_devs.h> #include <soc/spi.h> +#include <spi-generic.h> static inline uint16_t spi_read_hsfs(pch_spi_regs * const regs) { @@ -181,7 +181,7 @@ void spi_release_bus(struct spi_slave *slave) /* Handled by PCH automatically. */ } -int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) +int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len) { u32 start, end, erase_size; int ret = 0; @@ -192,8 +192,6 @@ int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) return -1; } - flash->spi->rw = SPI_WRITE_FLAG; - start = offset; end = start + len; @@ -231,7 +229,8 @@ static void pch_read_data(uint8_t *data, int len) } } -int pch_hwseq_read(struct spi_flash *flash, u32 addr, size_t len, void *buf) +int pch_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, + void *buf) { uint8_t block_len; @@ -292,8 +291,8 @@ static void pch_fill_data(const uint8_t *data, int len) writel_(temp32, (uint8_t *)spi_bar->fdata + (i - (i % 4))); } -int pch_hwseq_write(struct spi_flash *flash, - u32 addr, size_t len, const void *buf) +int pch_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, + const void *buf) { uint8_t block_len; uint32_t start = addr; @@ -330,7 +329,7 @@ int pch_hwseq_write(struct spi_flash *flash, return 0; } -int pch_hwseq_read_status(struct spi_flash *flash, u8 *reg) +int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg) { size_t block_len = SPI_READ_STATUS_LENGTH; const int timeout_ms = 6; @@ -358,10 +357,10 @@ static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi) flash->spi = spi; flash->name = "Opaque HW-sequencing"; - flash->write = pch_hwseq_write; - flash->erase = pch_hwseq_erase; - flash->read = pch_hwseq_read; - flash->status = pch_hwseq_read_status; + flash->internal_write = pch_hwseq_write; + flash->internal_erase = pch_hwseq_erase; + flash->internal_read = pch_hwseq_read; + flash->internal_status = pch_hwseq_read_status; /* The hardware sequencing supports 4KiB or 64KiB erase. Use 4KiB. */ flash->sector_size = 4*KiB; diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h index 49d60b0cd4..00500670fe 100644 --- a/src/soc/intel/skylake/include/soc/flash_controller.h +++ b/src/soc/intel/skylake/include/soc/flash_controller.h @@ -21,13 +21,12 @@ #include <console/console.h> #include <spi_flash.h> -int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len); -int pch_hwseq_write(struct spi_flash *flash, - u32 addr, size_t len, const void *buf); - -int pch_hwseq_read(struct spi_flash *flash, - u32 addr, size_t len, void *buf); -int pch_hwseq_read_status(struct spi_flash *flash, u8 *reg); +int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len); +int pch_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, + const void *buf); +int pch_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, + void *buf); +int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg); #if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c index db69cbeab7..16224046d7 100644 --- a/src/soc/intel/skylake/romstage/spi.c +++ b/src/soc/intel/skylake/romstage/spi.c @@ -16,6 +16,7 @@ #include <soc/flash_controller.h> #include <soc/romstage.h> +#include <spi-generic.h> /* * Minimal set of commands to read WPSR from SPI. |