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-rw-r--r--src/soc/intel/apollolake/pmc.c98
-rw-r--r--src/soc/intel/common/block/include/intelblocks/pmc.h67
-rw-r--r--src/soc/intel/common/block/pmc/Makefile.inc13
-rw-r--r--src/soc/intel/common/block/pmc/pmc.c117
-rw-r--r--src/soc/intel/skylake/Makefile.inc1
-rw-r--r--src/soc/intel/skylake/pmc.c140
-rw-r--r--src/soc/intel/skylake/romstage/Makefile.inc1
-rw-r--r--src/soc/intel/skylake/romstage/pmc.c30
8 files changed, 248 insertions, 219 deletions
diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c
index a4b91e1b64..58cb71a43f 100644
--- a/src/soc/intel/apollolake/pmc.c
+++ b/src/soc/intel/apollolake/pmc.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2016-2017 Intel Corp.
* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
@@ -15,74 +15,27 @@
* GNU General Public License for more details.
*/
+#include "chip.h"
+#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
+#include <intelblocks/pmc.h>
#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
-#include <soc/gpio.h>
-#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <timer.h>
-#include "chip.h"
-/*
- * The ACPI IO BAR (offset 0x20) is not PCI compliant. We've observed cases
- * where the BAR reads back as 0, but the IO window is open. This also means
- * that it will not respond to PCI probing. In the event that probing the BAR
- * fails, we still need to create a resource for it.
- */
-static void read_resources(device_t dev)
+/* Fill up PMC resource structure */
+int pmc_soc_get_resources(struct pmc_resource_config *cfg)
{
- struct resource *res;
- pci_dev_read_resources(dev);
-
- res = new_resource(dev, PCI_BASE_ADDRESS_0);
- res->base = PMC_BAR0;
- res->size = PMC_BAR0_SIZE;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
- res = new_resource(dev, PCI_BASE_ADDRESS_4);
- res->base = ACPI_BASE_ADDRESS;
- res->size = ACPI_BASE_SIZE;
- res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-/*
- * Part 2:
- * Resources are assigned, and no other device was given an IO resource to
- * overlap with our ACPI BAR. But because the resource is FIXED,
- * pci_dev_set_resources() will not store it for us. We need to do that
- * explicitly.
- */
-static void set_resources(device_t dev)
-{
- struct resource *res;
-
- pci_dev_set_resources(dev);
-
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- pci_write_config32(dev, res->index, res->base);
- dev->command |= PCI_COMMAND_MEMORY;
- res->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, res, " PMC BAR");
-
- res = find_resource(dev, PCI_BASE_ADDRESS_4);
- pci_write_config32(dev, res->index, res->base);
- dev->command |= PCI_COMMAND_IO;
- res->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, res, " ACPI BAR");
-}
-
-static void pch_set_acpi_mode(void)
-{
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
- printk(BIOS_DEBUG, "Disabling ACPI via APMC:");
- outb(APM_CNT_ACPI_DISABLE, APM_CNT);
- printk(BIOS_DEBUG, "Done.\n");
- }
+ cfg->pwrmbase_offset = PCI_BASE_ADDRESS_0;
+ cfg->pwrmbase_addr = PMC_BAR0;
+ cfg->pwrmbase_size = PMC_BAR0_SIZE;
+ cfg->abase_offset = PCI_BASE_ADDRESS_4;
+ cfg->abase_addr = ACPI_BASE_ADDRESS;
+ cfg->abase_size = ACPI_BASE_SIZE;
+
+ return 0;
}
static int choose_slp_s3_assertion_width(int width_usecs)
@@ -138,14 +91,14 @@ static void set_slp_s3_assertion_width(int width_usecs)
write32((void *)gen_pmcon3, reg);
}
-static void pmc_init(struct device *dev)
+void pmc_soc_init(struct device *dev)
{
const struct soc_intel_apollolake_config *cfg = dev->chip_info;
/* Set up GPE configuration */
pmc_gpe_init();
pmc_fixup_power_state();
- pch_set_acpi_mode();
+ pmc_set_acpi_mode();
if (cfg != NULL)
set_slp_s3_assertion_width(cfg->slp_s3_assertion_width_usecs);
@@ -156,22 +109,3 @@ static void pmc_init(struct device *dev)
/* Now that things have been logged clear out the PMC state. */
pmc_clear_prsts();
}
-
-static const struct device_operations device_ops = {
- .read_resources = read_resources,
- .set_resources = set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = &pmc_init,
-};
-
-static const unsigned short pci_device_ids[] = {
- PCI_DEVICE_ID_INTEL_APL_PMC,
- PCI_DEVICE_ID_INTEL_GLK_PMC,
- 0,
-};
-
-static const struct pci_driver pmc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .devices= pci_device_ids,
-};
diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h
new file mode 100644
index 0000000000..850cda178b
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/pmc.h
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_PMC_H
+#define SOC_INTEL_COMMON_BLOCK_PMC_H
+
+#include <device/device.h>
+#include <stdint.h>
+
+/* PMC controller resource structure */
+struct pmc_resource_config {
+ /* PMC PCI config offset for MMIO BAR */
+ uint8_t pwrmbase_offset;
+ /* MMIO BAR address */
+ uintptr_t pwrmbase_addr;
+ /* MMIO BAR size */
+ size_t pwrmbase_size;
+ /* PMC PCI config offset for IO BAR */
+ uint8_t abase_offset;
+ /* IO BAR address */
+ uintptr_t abase_addr;
+ /* IO BAR size */
+ size_t abase_size;
+};
+
+/*
+ * SoC overrides
+ *
+ * All new SoCs wishes to make use of common PMC PCI driver
+ * must implement below functionality .
+ */
+
+/*
+ * Function to initialize PMC controller.
+ *
+ * This initialization may differ between different SoC
+ *
+ * Input: Device Structure PMC PCI device
+ */
+void pmc_soc_init(struct device *dev);
+
+/*
+ * SoC should fill this structure information based on
+ * PMC controller register information like PWRMBASE, ABASE offset
+ * BAR and Size
+ *
+ * Input: PMC config structure
+ * Output: -1 = Error, 0 = Success
+ */
+int pmc_soc_get_resources(struct pmc_resource_config *cfg);
+
+/* API to set ACPI mode */
+void pmc_set_acpi_mode(void);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_PMC_H */
diff --git a/src/soc/intel/common/block/pmc/Makefile.inc b/src/soc/intel/common/block/pmc/Makefile.inc
index 40fcba10f7..225311599d 100644
--- a/src/soc/intel/common/block/pmc/Makefile.inc
+++ b/src/soc/intel/common/block/pmc/Makefile.inc
@@ -1,5 +1,8 @@
-bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
-romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
-ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
-smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
-verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
+ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC),y)
+bootblock-y += pmclib.c
+romstage-y += pmclib.c
+ramstage-y += pmc.c
+ramstage-y += pmclib.c
+smm-y += pmclib.c
+verstage-y += pmclib.c
+endif
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
new file mode 100644
index 0000000000..708e70572a
--- /dev/null
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <intelblocks/pmc.h>
+#include <soc/pci_devs.h>
+
+/* SoC overrides */
+
+/* Fill up PMC resource structure inside SoC directory */
+__attribute__((weak)) int pmc_soc_get_resources(
+ struct pmc_resource_config *cfg)
+{
+ /* no-op */
+ return -1;
+}
+
+/* SoC override PMC initialization */
+__attribute__((weak)) void pmc_soc_init(struct device *dev)
+{
+ /* no-op */
+}
+
+static void pch_pmc_add_new_resource(struct device *dev,
+ uint8_t offset, uintptr_t base, size_t size,
+ unsigned long flags)
+{
+ struct resource *res;
+ res = new_resource(dev, offset);
+ res->base = base;
+ res->size = size;
+ res->flags = flags;
+}
+
+static void pch_pmc_add_mmio_resources(struct device *dev,
+ const struct pmc_resource_config *cfg)
+{
+ pch_pmc_add_new_resource(dev, cfg->pwrmbase_offset,
+ cfg->pwrmbase_addr, cfg->pwrmbase_size,
+ IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+ IORESOURCE_FIXED | IORESOURCE_RESERVE);
+}
+
+static void pch_pmc_add_io_resources(struct device *dev,
+ const struct pmc_resource_config *cfg)
+{
+ pch_pmc_add_new_resource(dev, cfg->abase_offset,
+ cfg->abase_addr, cfg->abase_size,
+ IORESOURCE_IO | IORESOURCE_ASSIGNED |
+ IORESOURCE_FIXED);
+}
+
+static void pch_pmc_read_resources(struct device *dev)
+{
+ struct pmc_resource_config pmc_cfg;
+ struct pmc_resource_config *config = &pmc_cfg;
+
+ if (pmc_soc_get_resources(config) < 0)
+ die("Unable to get PMC controller resource information!");
+
+ /* Get the normal PCI resources of this device. */
+ pci_dev_read_resources(dev);
+
+ /* Add non-standard MMIO resources. */
+ pch_pmc_add_mmio_resources(dev, config);
+
+ /* Add IO resources. */
+ pch_pmc_add_io_resources(dev, config);
+}
+
+void pmc_set_acpi_mode(void)
+{
+ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
+ printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
+ outb(APM_CNT_ACPI_DISABLE, APM_CNT);
+ printk(BIOS_DEBUG, "done.\n");
+ }
+}
+
+static struct device_operations device_ops = {
+ .read_resources = &pch_pmc_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+ .init = &pmc_soc_init,
+ .scan_bus = &scan_lpc_bus,
+};
+
+static const unsigned short pci_device_ids[] = {
+ PCI_DEVICE_ID_INTEL_SPT_LP_PMC,
+ PCI_DEVICE_ID_INTEL_KBP_H_PMC,
+ PCI_DEVICE_ID_INTEL_APL_PMC,
+ PCI_DEVICE_ID_INTEL_GLK_PMC,
+ 0
+};
+
+static const struct pci_driver pch_lpc __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index b5fae3de8d..c40f6e12ce 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -37,6 +37,7 @@ romstage-y += memmap.c
romstage-y += me.c
romstage-y += pch.c
romstage-y += pei_data.c
+romstage-y += pmc.c
romstage-y += pmutil.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
romstage-y += spi.c
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index 9c05ff6c27..91b319c55b 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -3,7 +3,7 @@
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,25 +18,40 @@
#include <chip.h>
#include <console/console.h>
#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include <arch/acpi.h>
-#include <cpu/cpu.h>
-#include <intelblocks/pcr.h>
+#include <intelblocks/pmc.h>
#include <intelblocks/pmclib.h>
-#include <pc80/mc146818rtc.h>
+#include <intelblocks/rtc.h>
#include <reg_script.h>
-#include <string.h>
-#include <soc/gpio.h>
-#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
-#include <soc/pmc.h>
-#include <cpu/x86/smm.h>
-#include <soc/pcr_ids.h>
-#include <soc/ramstage.h>
+
+void pmc_set_disb(void)
+{
+ /* Set the DISB after DRAM init */
+ u32 disb_val;
+ device_t dev = PCH_DEV_PMC;
+
+ disb_val = pci_read_config32(dev, GEN_PMCON_A);
+ disb_val |= DISB;
+
+ /* Don't clear bits that are write-1-to-clear */
+ disb_val &= ~(GBL_RST_STS | MS4V);
+ pci_write_config32(dev, GEN_PMCON_A, disb_val);
+}
+
+#if ENV_RAMSTAGE
+/* Fill up PMC resource structure */
+int pmc_soc_get_resources(struct pmc_resource_config *cfg)
+{
+ cfg->pwrmbase_offset = PWRMBASE;
+ cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS;
+ cfg->pwrmbase_size = PCH_PWRM_BASE_SIZE;
+ cfg->abase_offset = ABASE;
+ cfg->abase_addr = ACPI_BASE_ADDRESS;
+ cfg->abase_size = ACPI_BASE_SIZE;
+
+ return 0;
+}
static const struct reg_script pch_pmc_misc_init_script[] = {
/* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */
@@ -58,68 +73,11 @@ static const struct reg_script pmc_write1_to_clear_script[] = {
REG_SCRIPT_END
};
-static void pch_pmc_add_mmio_resources(device_t dev)
-{
- struct resource *res;
-
- /* Memory-mmapped I/O registers. */
- res = new_resource(dev, PWRMBASE);
- res->base = PCH_PWRM_BASE_ADDRESS;
- res->size = PCH_PWRM_BASE_SIZE;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
- IORESOURCE_FIXED | IORESOURCE_RESERVE;
-}
-
-static void pch_pmc_add_io_resource(device_t dev, u16 base, u16 size, int index)
-{
- struct resource *res;
- res = new_resource(dev, index);
- res->base = base;
- res->size = size;
- res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static void pch_pmc_add_io_resources(device_t dev)
-{
- /* PMBASE */
- pch_pmc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);
-}
-
-static void pch_pmc_read_resources(device_t dev)
-{
- /* Get the normal PCI resources of this device. */
- pci_dev_read_resources(dev);
-
- /* Add non-standard MMIO resources. */
- pch_pmc_add_mmio_resources(dev);
-
- /* Add IO resources. */
- pch_pmc_add_io_resources(dev);
-}
-
-static void pch_set_acpi_mode(void)
-{
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
- printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
- outb(APM_CNT_ACPI_DISABLE, APM_CNT);
- printk(BIOS_DEBUG, "done.\n");
- }
-}
-
-static void pch_rtc_init(void)
-{
- /* Ensure the date is set including century byte. */
- cmos_check_update_date();
-
- cmos_init(rtc_failure());
-}
-
-static void pch_power_options(void)
+static void pch_power_options(struct device *dev)
{
u16 reg16;
const char *state;
- /*PMC Controller Device 0x1F, Func 02*/
- device_t dev = PCH_DEV_PMC;
+
/* Get the chip configuration */
int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
@@ -199,19 +157,19 @@ static void config_deep_sx(uint32_t deepsx_config)
write32(pmcbase + DSX_CFG, reg);
}
-static void pmc_init(struct device *dev)
+void pmc_soc_init(struct device *dev)
{
- config_t *config = dev->chip_info;
+ const config_t *config = dev->chip_info;
- pch_rtc_init();
+ rtc_init();
/* Initialize power management */
- pch_power_options();
+ pch_power_options(dev);
/* Note that certain bits may be cleared from running script as
* certain bit fields are write 1 to clear. */
reg_script_run_on_dev(dev, pch_pmc_misc_init_script);
- pch_set_acpi_mode();
+ pmc_set_acpi_mode();
config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
@@ -220,24 +178,4 @@ static void pmc_init(struct device *dev)
/* Clear registers that contain write-1-to-clear bits. */
reg_script_run_on_dev(dev, pmc_write1_to_clear_script);
}
-
-static struct device_operations device_ops = {
- .read_resources = &pch_pmc_read_resources,
- .set_resources = &pci_dev_set_resources,
- .enable_resources = &pci_dev_enable_resources,
- .init = &pmc_init,
- .scan_bus = &scan_lpc_bus,
- .ops_pci = &soc_pci_ops,
-};
-
-static const unsigned short pci_device_ids[] = {
- 0x9d21,
- 0xa121,
- 0
-};
-
-static const struct pci_driver pch_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .devices = pci_device_ids,
-};
+#endif
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 6dbe718e0b..8bfbfea66a 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,5 +1,4 @@
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S
-romstage-y += pmc.c
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
romstage-y += systemagent.c
diff --git a/src/soc/intel/skylake/romstage/pmc.c b/src/soc/intel/skylake/romstage/pmc.c
deleted file mode 100644
index e9d06f2c31..0000000000
--- a/src/soc/intel/skylake/romstage/pmc.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-
-void pmc_set_disb(void)
-{
- /* Set the DISB after DRAM init */
- u32 disb_val = 0;
- pci_devfn_t dev = PCH_DEV_PMC;
- disb_val = pci_read_config32(dev, GEN_PMCON_A);
- disb_val |= DISB;
-
- /* Don't clear bits that are write-1-to-clear */
- disb_val &= ~(GBL_RST_STS | MS4V);
- pci_write_config32(dev, GEN_PMCON_A, disb_val);
-}