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-rw-r--r--src/soc/intel/cannonlake/chip.h8
-rw-r--r--src/soc/intel/cannonlake/romstage/romstage.c2
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 48305fe642..0ed41fc824 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -186,6 +186,14 @@ struct soc_intel_cannonlake_config {
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
uint8_t eist_enable;
+ /* Enable C6 DRAM */
+ uint8_t enable_c6dram;
+ /*
+ * PRMRR size setting with below options
+ * 0x00100000 - 1MiB
+ * 0x02000000 - 32MiB and beyond
+ */
+ uint32_t PrmrrSize;
};
typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 17c31910e9..5fa39ca933 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -82,6 +82,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
mask |= (1 << i);
}
m_cfg->PcieRpEnableMask = mask;
+ m_cfg->PrmrrSize = config->PrmrrSize;
+ m_cfg->EnableC6Dram = config->enable_c6dram;
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)