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-rw-r--r--src/soc/intel/apollolake/Makefile.inc4
-rw-r--r--src/soc/intel/baytrail/Kconfig11
-rw-r--r--src/soc/intel/braswell/Kconfig11
-rw-r--r--src/soc/intel/broadwell/Kconfig10
4 files changed, 2 insertions, 34 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index d63316969b..1fbdc91c72 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -74,8 +74,8 @@ ramstage-y += xhci.c
postcar-y += mmap_boot.c
postcar-y += spi.c
postcar-y += i2c.c
-postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c
-postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c
+postcar-y += heci.c
+postcar-y += reset.c
postcar-y += uart.c
postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += gspi.c
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 94ed887d5c..4e9223750e 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -124,17 +124,6 @@ config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
-config RESET_ON_INVALID_RAMSTAGE_CACHE
- bool "Reset the system on S3 wake when ramstage cache invalid."
- default n
- help
- The baytrail romstage code caches the loaded ramstage program
- in SMM space. On S3 wake the romstage will copy over a fresh
- ramstage that was cached in the SMM space. This option determines
- the action to take when the ramstage cache is invalid. If selected
- the system will reset otherwise the ramstage will be reloaded from
- cbfs.
-
config ENABLE_BUILTIN_COM1
bool "Enable builtin COM1 Serial Port"
default n
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index ba2ac68bf8..5b6a9237e7 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -104,17 +104,6 @@ config DCACHE_RAM_SIZE
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.
-config RESET_ON_INVALID_RAMSTAGE_CACHE
- bool "Reset the system on S3 wake when ramstage cache invalid."
- default n
- help
- The haswell romstage code caches the loaded ramstage program
- in SMM space. On S3 wake the romstage will copy over a fresh
- ramstage that was cached in the SMM space. This option determines
- the action to take when the ramstage cache is invalid. If selected
- the system will reset otherwise the ramstage will be reloaded from
- cbfs.
-
config ENABLE_BUILTIN_COM1
bool "Enable builtin COM1 Serial Port"
default n
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 21c9b6f12a..f01777f4f0 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -166,16 +166,6 @@ config PRE_GRAPHICS_DELAY
VBIOS. On those systems we need to wait for a bit before executing
the VBIOS.
-config RESET_ON_INVALID_RAMSTAGE_CACHE
- bool "Reset the system on S3 wake when ramstage cache invalid."
- default n
- help
- The romstage code caches the loaded ramstage program in SMM space.
- On S3 wake the romstage will copy over a fresh ramstage that was
- cached in the SMM space. This option determines the action to take
- when the ramstage cache is invalid. If selected the system will
- reset otherwise the ramstage will be reloaded from cbfs.
-
config INTEL_PCH_UART_CONSOLE
bool "Use Serial IO UART for console"
default n