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-rw-r--r--src/soc/intel/denverton_ns/acpi/northcluster.asl2
-rw-r--r--src/soc/intel/denverton_ns/include/soc/iomap.h1
2 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl
index bbfa13313a..f212557a56 100644
--- a/src/soc/intel/denverton_ns/acpi/northcluster.asl
+++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl
@@ -138,7 +138,7 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() {
// PCIEXBAR memory range
- Memory32Fixed(ReadOnly, DEFAULT_PCIEXBAR, 0x10000000)
+ Memory32Fixed(ReadOnly, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000)
// TSEG
Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB)
})
diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h
index a7548d40a3..8bcef91c2e 100644
--- a/src/soc/intel/denverton_ns/include/soc/iomap.h
+++ b/src/soc/intel/denverton_ns/include/soc/iomap.h
@@ -23,7 +23,6 @@
*/
/* Northbridge BARs */
-#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
/* Southbridge internal device IO BARs (Set to match FSP settings) */