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-rw-r--r--src/soc/intel/tigerlake/Kconfig2
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c20
2 files changed, 21 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 091abb927f..51c379dff2 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -32,7 +32,7 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED
- select PLATFORM_USES_FSP2_1
+ select PLATFORM_USES_FSP2_2
select FSP_PEIM_TO_PEIM_INTERFACE
select REG_SCRIPT
select SMP
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 798c16a425..cf24021841 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -327,9 +327,29 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
}
+ /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */
+ params->EnableMultiPhaseSiliconInit = 1;
mainboard_silicon_init_params(params);
}
+/*
+ * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit
+ * This platform supports below MultiPhaseSIInit Phase(s):
+ * Phase | FSP return point | Purpose
+ * ------- + ------------------------------------------------ + -------------------------------
+ * 1 | After TCSS initialization completed | for TCSS specific init
+ */
+void platform_fsp_multi_phase_init_cb(uint32_t phase_index)
+{
+ switch (phase_index) {
+ case 1:
+ /* TCSS specific initialization here */
+ break;
+ default:
+ break;
+ }
+}
+
/* Mainboard GPIO Configuration */
__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{