diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/broadwell/acpi.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/bootblock/pch.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/bootblock/systemagent.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/broadwell/rcba.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/broadwell/smm.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/broadwell/spi.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/cpu.c | 10 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/lpc.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/me_status.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/pch.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/pcie.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/spi.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/smihandler.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/spi.c | 6 |
14 files changed, 24 insertions, 24 deletions
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 6d41ae67df..5e7b72b377 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -44,7 +44,7 @@ #include <chip.h> /* - * List of suported C-states in this processor. Only the ULT parts support C8, + * List of supported C-states in this processor. Only the ULT parts support C8, * C9, and C10. */ enum { diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index 9e76f7976f..2475a25955 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -55,7 +55,7 @@ static void map_rcba(void) static void enable_port80_on_lpc(void) { - /* Enable port 80 POST on LPC. The chipset does this by deafult, + /* Enable port 80 POST on LPC. The chipset does this by default, * but it doesn't appear to hurt anything. */ u32 gcs = RCBA32(GCS); gcs = gcs & ~0x4; diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index b2dd27b1a1..b5f82b21b4 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -32,7 +32,7 @@ static void bootblock_northbridge_init(void) * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/soc/intel/broadwell/broadwell/rcba.h b/src/soc/intel/broadwell/broadwell/rcba.h index f2c7343199..6737fe9940 100644 --- a/src/soc/intel/broadwell/broadwell/rcba.h +++ b/src/soc/intel/broadwell/broadwell/rcba.h @@ -36,7 +36,7 @@ #define RPC 0x0400 /* 32bit */ #define RPFN 0x0404 /* 32bit */ -/* Root Port configuratinon space hide */ +/* Root Port configuration space hide */ #define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) /* Get the function number assigned to a Root Port */ #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) diff --git a/src/soc/intel/broadwell/broadwell/smm.h b/src/soc/intel/broadwell/broadwell/smm.h index a6d896f042..f7f515cd9b 100644 --- a/src/soc/intel/broadwell/broadwell/smm.h +++ b/src/soc/intel/broadwell/broadwell/smm.h @@ -48,7 +48,7 @@ struct smm_relocation_params { /* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig * is included after chipset code. This causes the chipset's Kconfig to be - * cloberred by the arch/x86/Kconfig if they have the same name. */ + * clobbered by the arch/x86/Kconfig if they have the same name. */ static inline int smm_region_size(void) { /* Make it 8MiB by default. */ @@ -64,7 +64,7 @@ void smm_relocate(void); void southbridge_trigger_smi(void); void southbridge_clear_smi_status(void); -/* The initialization of the southbridge is split into 2 compoments. One is +/* The initialization of the southbridge is split into 2 components. One is * for clearing the state in the SMM registers. The other is for enabling * SMIs. They are split so that other work between the 2 actions. */ void southbridge_smm_clear_state(void); diff --git a/src/soc/intel/broadwell/broadwell/spi.h b/src/soc/intel/broadwell/broadwell/spi.h index 888452547e..8b95f70a5f 100644 --- a/src/soc/intel/broadwell/broadwell/spi.h +++ b/src/soc/intel/broadwell/broadwell/spi.h @@ -30,7 +30,7 @@ #define SPIBAR16(x) RCBA16(x + SPIBAR_OFFSET) #define SPIBAR32(x) RCBA32(x + SPIBAR_OFFSET) -/* Reigsters within the SPIBAR */ +/* Registers within the SPIBAR */ #define SPIBAR_SSFC 0x91 #define SPIBAR_FDOC 0xb0 #define SPIBAR_FDOD 0xb4 diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 58f81fc79d..afd2dcbb60 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -448,7 +448,7 @@ static void configure_thermal_target(void) config_t *conf = dev->chip_info; msr_t msr; - /* Set TCC activaiton offset if supported */ + /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & (1 << 30)) && conf->tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); @@ -688,8 +688,8 @@ void broadwell_init_cpus(device_t dev) ht_disabled = num_threads == num_cores; - /* Perform any necesarry BSP initialization before APs are brought up. - * This call alos allows the BSP to prepare for any secondary effects + /* Perform any necessary BSP initialization before APs are brought up. + * This call also allows the BSP to prepare for any secondary effects * from calling cpu_initialize() such as smm_init(). */ bsp_init_before_ap_bringup(cpu_bus); @@ -708,9 +708,9 @@ void broadwell_init_cpus(device_t dev) mp_params.num_records = ARRAY_SIZE(mp_steps); mp_params.microcode_pointer = microcode_patch; - /* Load relocation and permeanent handlers. Then initiate relocation. */ + /* Load relocation and permanent handlers. Then initiate relocation. */ if (smm_initialize()) - printk(BIOS_CRIT, "SMM Initialiazation failed...\n"); + printk(BIOS_CRIT, "SMM initialization failed...\n"); if (mp_init(cpu_bus, &mp_params)) { printk(BIOS_ERR, "MP initialization failure.\n"); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 76a136824d..394a9d7bdd 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -502,7 +502,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) { /* * Check if the register is enabled. If so and the base exceeds the - * device's deafult claim range add the resoure. + * device's default claim range add the resource. */ if (reg_value & 1) { u16 base = reg_value & 0xfffc; diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c index 40078b97d4..3738fd4c8b 100644 --- a/src/soc/intel/broadwell/me_status.c +++ b/src/soc/intel/broadwell/me_status.c @@ -178,7 +178,7 @@ static const char *me_progress_bup_values[] = { /* Progress Code 3 states */ static const char *me_progress_policy_values[] = { - [ME_HFS2_STATE_POLICY_ENTRY] = "Entery into Policy Module", + [ME_HFS2_STATE_POLICY_ENTRY] = "Entry into Policy Module", [ME_HFS2_STATE_POLICY_RCVD_S3] = "Received S3 entry", [ME_HFS2_STATE_POLICY_RCVD_S4] = "Received S4 entry", [ME_HFS2_STATE_POLICY_RCVD_S5] = "Received S5 entry", diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 82390a470b..492d177b53 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -88,7 +88,7 @@ static void pch_enable_d3hot(device_t dev) pci_write_config32(dev, PCH_PCS, reg32); } -/* Set bit in Function Disble register to hide this device */ +/* Set bit in Function Disable register to hide this device */ void pch_disable_devfn(device_t dev) { switch (dev->path.pci.devfn) { diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index a407f3c686..f167ca3bf4 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -417,21 +417,21 @@ static void pch_pcie_early(struct device *dev) case 3: case 4: /* - * Bits 31:28 of b0d28f0 0x32c register correspnd to + * Bits 31:28 of b0d28f0 0x32c register correspond to * Root Ports 4:1. */ do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1))); break; case 5: /* - * Bit 28 of b0d28f4 0x32c register correspnd to + * Bit 28 of b0d28f4 0x32c register correspond to * Root Ports 4:1. */ do_aspm = !!(rpc.b0d28f4_32c & (1 << 28)); break; case 6: /* - * Bit 28 of b0d28f5 0x32c register correspnd to + * Bit 28 of b0d28f5 0x32c register correspond to * Root Ports 4:1. */ do_aspm = !!(rpc.b0d28f5_32c & (1 << 28)); @@ -509,7 +509,7 @@ static void pch_pcie_early(struct device *dev) pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854c74); - /* Set Invalid Recieve Range Check Enable in MPC register. */ + /* Set Invalid Receive Range Check Enable in MPC register. */ pcie_update_cfg(dev, 0xd8, ~0, (1 << 25)); pcie_update_cfg8(dev, 0xf5, 0x3f, 0); diff --git a/src/soc/intel/broadwell/romstage/spi.c b/src/soc/intel/broadwell/romstage/spi.c index dd060b66d3..75df2fd1ca 100644 --- a/src/soc/intel/broadwell/romstage/spi.c +++ b/src/soc/intel/broadwell/romstage/spi.c @@ -50,7 +50,7 @@ static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) SPIBAR16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) | SPIBAR_HSFC_CYCLE_READ; - /* Start transactinon */ + /* Start transaction */ SPIBAR16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO; /* Wait for completion */ diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 85a4f47e44..064a9dcca4 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -537,7 +537,7 @@ void southbridge_smi_handler(void) southbridge_smi[i](); } else { printk(BIOS_DEBUG, - "SMI_STS[%d] occured, but no " + "SMI_STS[%d] occurred, but no " "handler available.\n", i); } } diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 353323a073..935c53215e 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -549,7 +549,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, /* * This is a 'no data' command (like Write Enable), its - * bitesout size was 1, decremented to zero while executing + * bytesout size was 1, decremented to zero while executing * spi_setup_opcode() above. Tell the chip to send the * command. */ @@ -569,7 +569,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, } /* - * Check if this is a write command atempting to transfer more bytes + * Check if this is a write command attempting to transfer more bytes * than the controller can handle. Iterations for writes are not * supported here because each SPI write command needs to be preceded * and followed by other SPI commands, and this sequence is controlled @@ -588,7 +588,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, while (trans.bytesout || trans.bytesin) { uint32_t data_length; - /* SPI addresses are 24 bit only */ + /* SPI addresses are 24 bit only */http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-n3520-j2850-celeron-n2920-n2820-n2815-n2806-j1850-j1750-datasheet.pdf writel_(trans.offset & 0x00FFFFFF, cntlr.addr); if (trans.bytesout) |