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-rw-r--r--src/soc/mediatek/mt8173/Makefile.inc4
-rw-r--r--src/soc/mediatek/mt8173/include/soc/mt6391.h67
-rw-r--r--src/soc/mediatek/mt8173/mt6391.c17
3 files changed, 72 insertions, 16 deletions
diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc
index efcc03214d..d5b450a75f 100644
--- a/src/soc/mediatek/mt8173/Makefile.inc
+++ b/src/soc/mediatek/mt8173/Makefile.inc
@@ -56,11 +56,13 @@ romstage-y += mmu_operations.c
ramstage-y += cbmem.c
ramstage-y += spi.c
ramstage-y += cbfs.c
-ramstage-y += soc.c
+ramstage-y += soc.c mtcmos.c
ramstage-y += timer.c
ramstage-$(CONFIG_DRIVERS_UART) += uart.c
+ramstage-y += pmic_wrap.c mt6391.c
ramstage-y += gpio.c
ramstage-y += wdt.c
+ramstage-y += pll.c
################################################################################
diff --git a/src/soc/mediatek/mt8173/include/soc/mt6391.h b/src/soc/mediatek/mt8173/include/soc/mt6391.h
index f3224a0a5e..392ad634a7 100644
--- a/src/soc/mediatek/mt8173/include/soc/mt6391.h
+++ b/src/soc/mediatek/mt8173/include/soc/mt6391.h
@@ -262,21 +262,14 @@ enum{
};
enum ldo_power {
- LDO_VCAMD,
- LDO_VCAMIO,
- LDO_VCAMAF,
- LDO_VGP4,
- LDO_VGP5,
- LDO_VGP6,
- LDO_VTCXO,
- LDO_VA28,
- LDO_VCAMA,
- LDO_VIO28,
- LDO_VUSB,
- LDO_VMC,
- LDO_VMCH,
- LDO_VEMC3V3,
- LDO_VIBR,
+ LDO_VCAMD = 0, /* VGP1 */
+ LDO_VCAMIO = 1, /* VGP2 */
+ LDO_VCAMAF = 2, /* VGP3 */
+ LDO_VGP4 = 3,
+ LDO_VGP5 = 4,
+ LDO_VGP6 = 5,
+ /* special, not part of main register set */
+ LDO_VCAMA = 6,
};
enum ldo_voltage {
@@ -326,6 +319,50 @@ enum mt6391_pull_select {
MT6391_GPIO_PULL_UP = 1,
};
+enum {
+ MT6391_PMU_INT = 0,
+ MT6391_SRCVOLTEN = 1,
+ MT6391_SRCLKEN_PERI = 2,
+ MT6391_RTC32K_1V8 = 3,
+ MT6391_WRAP_EVENT = 4,
+ MT6391_SPI_CLK = 5,
+ MT6391_SPI_CSN = 6,
+ MT6391_SPI_MOSI = 7,
+ MT6391_SPI_MISO = 8,
+ MT6391_AUD_CLK_MOSI = 9,
+ MT6391_AUD_DAT_MISO = 10,
+ MT6391_AUD_DAT_MOSI = 11,
+ MT6391_KP_COL0 = 12,
+ MT6391_KP_COL1 = 13,
+ MT6391_KP_COL2 = 14,
+ MT6391_KP_COL3 = 15,
+ MT6391_KP_COL4 = 16,
+ MT6391_KP_COL5 = 17,
+ MT6391_KP_COL6 = 18,
+ MT6391_KP_COL7 = 19,
+ MT6391_KP_ROW0 = 20,
+ MT6391_KP_ROW1 = 21,
+ MT6391_KP_ROW2 = 22,
+ MT6391_KP_ROW3 = 23,
+ MT6391_KP_ROW4 = 24,
+ MT6391_KP_ROW5 = 25,
+ MT6391_KP_ROW6 = 26,
+ MT6391_KP_ROW7 = 27,
+ MT6391_VMSEL1 = 28,
+ MT6391_VMSEL2 = 29,
+ MT6391_PWM = 30,
+ MT6391_SCL0 = 31,
+ MT6391_SDA0 = 32,
+ MT6391_SCL1 = 33,
+ MT6391_SDA1 = 34,
+ MT6391_SCL2 = 35,
+ MT6391_SDA2 = 36,
+ MT6391_HDMISD = 37,
+ MT6391_HDMISCK = 38,
+ MT6391_HTPLG = 39,
+ MT6391_CEC = 40,
+};
+
/*
* PMIC GPIO Exported Function
*/
diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c
index 09f14a1597..21ce7ea6fe 100644
--- a/src/soc/mediatek/mt8173/mt6391.c
+++ b/src/soc/mediatek/mt8173/mt6391.c
@@ -59,6 +59,19 @@ void mt6391_write(u16 reg, u16 val, u32 mask, u32 shift)
return;
}
+static void mt6391_configure_vcama(enum ldo_voltage vsel)
+{
+ /* 2'b00: 1.5V
+ * 2'b01: 1.8V
+ * 2'b10: 2.5V
+ * 2'b11: 2.8V
+ */
+ mt6391_write(PMIC_RG_ANALDO_CON6, vsel - 2, PMIC_RG_VCAMA_VOSEL_MASK,
+ PMIC_RG_VCAMA_VOSEL_SHIFT);
+ mt6391_write(PMIC_RG_ANALDO_CON2, 1, PMIC_RG_VCAMA_EN_MASK,
+ PMIC_RG_VCAMA_EN_SHIFT);
+}
+
void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel)
{
u16 addr;
@@ -78,6 +91,10 @@ void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel)
if (vsel == LDO_2P0)
vsel = 7;
break;
+ case LDO_VCAMA:
+ assert(vsel > LDO_1P3 && vsel < LDO_3P0);
+ mt6391_configure_vcama(vsel);
+ return;
default:
break;
}