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Diffstat (limited to 'src/soc/nvidia/tegra124')
-rw-r--r--src/soc/nvidia/tegra124/i2c.c2
-rw-r--r--src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c6
-rw-r--r--src/soc/nvidia/tegra124/uart.c2
3 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/nvidia/tegra124/i2c.c b/src/soc/nvidia/tegra124/i2c.c
index 76b8f138f9..ee339bbe48 100644
--- a/src/soc/nvidia/tegra124/i2c.c
+++ b/src/soc/nvidia/tegra124/i2c.c
@@ -50,4 +50,4 @@ struct tegra_i2c_bus_info tegra_i2c_info[] = {
}
};
-unsigned g_num_i2c_buses = ARRAY_SIZE(tegra_i2c_info);
+unsigned int g_num_i2c_buses = ARRAY_SIZE(tegra_i2c_info);
diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
index e00dbd1039..0ebe8e7056 100644
--- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
@@ -292,7 +292,7 @@ static void __noreturn reset(void)
halt();
}
-static void udelay(unsigned usecs)
+static void udelay(unsigned int usecs)
{
uint32_t start = read32(timer_us_ptr);
while (read32(timer_us_ptr) - start < usecs)
@@ -313,7 +313,7 @@ static uint32_t get_wakeup_vector(void)
return read32(pmc_ctlr_scratch41_ptr);
}
-static unsigned get_osc_freq(void)
+static unsigned int get_osc_freq(void)
{
return (read32(clk_rst_osc_ctrl_ptr) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
}
@@ -507,7 +507,7 @@ void ram_repair(void)
/* Power. */
-static void power_on_partition(unsigned id)
+static void power_on_partition(unsigned int id)
{
uint32_t bit = 0x1 << id;
if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) {
diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c
index f5f72aff4b..9bebc72afb 100644
--- a/src/soc/nvidia/tegra124/uart.c
+++ b/src/soc/nvidia/tegra124/uart.c
@@ -45,7 +45,7 @@ static int tegra124_uart_tst_byte(struct tegra124_uart *uart_ptr);
static void tegra124_uart_init(struct tegra124_uart *uart_ptr)
{
// Use a hardcoded divisor for now.
- const unsigned divisor = 221;
+ const unsigned int divisor = 221;
const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1
tegra124_uart_tx_flush(uart_ptr);