diff options
Diffstat (limited to 'src/soc/nvidia/tegra124')
| -rw-r--r-- | src/soc/nvidia/tegra124/Kconfig | 24 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/bootblock.c | 13 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/verstage.c | 58 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra124/verstage.h | 2 |
4 files changed, 74 insertions, 23 deletions
diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index fddb6dadab..4fcc6b4440 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -38,6 +38,16 @@ config BOOTBLOCK_CPU_INIT # 0x4002_0000 Bootblock (max 48KB). # 0x4002_C000 ROM stage (max 80KB). # 0x4003_FFFF End of iRAM. +# +# if VBOOT2_VERIFY_FIRMWARE, +# 0x4000_0000 TTB (16K+32B). 32B is for L1 table of LPAE. +# 0x4000_4020 CBMEM console area (8K-32B) +# 0x4000_6000 CBFS mapping cache (72K) +# 0x4001_8000 vboot work buffer (16K) +# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!). +# 0x4002_0000 bootblock and romstage (max 70KB). +# 0x4003_1000 verstage (max 60KB). +# 0x4003_FFFF End of iRAM. config BOOTBLOCK_ROM_OFFSET hex @@ -45,12 +55,10 @@ config BOOTBLOCK_ROM_OFFSET config CBFS_HEADER_ROM_OFFSET hex "offset of master CBFS header in ROM" - default 0x1e000 if VBOOT2_VERIFY_FIRMWARE default 0x18000 config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" - default 0x1e080 if VBOOT2_VERIFY_FIRMWARE default 0x18080 config SYS_SDRAM_BASE @@ -61,9 +69,16 @@ config BOOTBLOCK_BASE hex default 0x40020000 +# this has to be big enough to leave room big enough for the larger of the +# bootblock and the romstage. +config VERSTAGE_BASE + hex + default 0x40031000 + +# with vboot2, romstage is loaded over to the bootblock space config ROMSTAGE_BASE hex - default 0x4002d000 if VBOOT2_VERIFY_FIRMWARE + default 0x40020000 if VBOOT2_VERIFY_FIRMWARE default 0x4002c000 config RAMSTAGE_BASE @@ -94,7 +109,8 @@ config CBFS_CACHE_ADDRESS config CBFS_CACHE_SIZE hex "size of CBFS cache data" - default 0x00017fe0 + default 0x00012000 if VBOOT2_VERIFY_FIRMWARE + default 0x00016000 config VBOOT_WORK_BUFFER_ADDRESS hex "memory address of vboot work buffer" diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index 1d18f1e4cf..f08ca413ad 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -18,18 +18,15 @@ */ #include <assert.h> -#include <arch/cache.h> #include <arch/exception.h> #include <bootblock_common.h> #include <cbfs.h> #include <console/console.h> #include <soc/clock.h> #include <soc/nvidia/tegra/apbmisc.h> -#include <soc/nvidia/tegra124/early_configs.h> #include <vendorcode/google/chromeos/chromeos.h> #include "pinmux.h" #include "power.h" -#include "verstage.h" void main(void) { @@ -73,11 +70,11 @@ void main(void) PINMUX_PWR_INT_N_FUNC_PMICINTR | PINMUX_INPUT_ENABLE); - if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)) { - early_mainboard_init(); - entry = (void *)verstage_vboot_main; - } else - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); + if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)) + entry = NULL; + else + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, + CONFIG_CBFS_PREFIX "/romstage"); ASSERT(entry); clock_cpu0_config(entry); diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index d85fc5c8cf..60361a2afd 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -1,15 +1,55 @@ -#include "verstage.h" +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/cache.h> +#include <arch/exception.h> +#include <console/console.h> +#include <soc/nvidia/tegra124/cache.h> +#include <soc/nvidia/tegra124/early_configs.h> #include <vendorcode/google/chromeos/chromeos.h> -/** - * Stage entry point - */ -void vboot_main(void) +static void enable_cache(void) +{ + mmu_init(); + /* Whole space is uncached. */ + mmu_config_range(0, 4096, DCACHE_OFF); + /* SRAM is cached. Round the size up to 2MB, the LPAE page size. */ + mmu_config_range(0x40000000 >> 20, 1, DCACHE_WRITEBACK); + mmu_disable_range(0, 1); + dcache_mmu_enable(); +} + +/* Do the minimum to run vboot at full speed */ +static void soc_init(void) +{ + configure_l2_cache(); + console_init(); + exception_init(); + enable_cache(); +} + +void main(void) { - /* Stub to force arm_init_caches to the top, before any stack/memory - * accesses */ asm volatile ("bl arm_init_caches" - ::: "r0","r1","r2","r3","r4","r5","ip"); + : : : "r0", "r1", "r2", "r3", "r4", "r5", "ip"); - select_firmware(); + soc_init(); + early_mainboard_init(); + vboot2_verify_firmware(); } diff --git a/src/soc/nvidia/tegra124/verstage.h b/src/soc/nvidia/tegra124/verstage.h deleted file mode 100644 index a0bac347c6..0000000000 --- a/src/soc/nvidia/tegra124/verstage.h +++ /dev/null @@ -1,2 +0,0 @@ -void vboot_main(void); -void verstage_vboot_main(void); |