diff options
Diffstat (limited to 'src/soc/nvidia/tegra132/i2c6.c')
| -rw-r--r-- | src/soc/nvidia/tegra132/i2c6.c | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/src/soc/nvidia/tegra132/i2c6.c b/src/soc/nvidia/tegra132/i2c6.c index 86373d621e..73a98562ad 100644 --- a/src/soc/nvidia/tegra132/i2c6.c +++ b/src/soc/nvidia/tegra132/i2c6.c @@ -83,14 +83,7 @@ void soc_configure_i2c6pad(void) * and put Host1X back in reset. DPAUX must remain out of * reset and the SOR partition must remained unpowergated. */ - power_ungate_partition(POWER_PARTID_SOR); - - /* Host1X needs a valid clock source so DPAUX can be accessed */ - clock_configure_source(host1x, PLLP, 204000); - - enable_sor_periph_clocks(); - remove_clamps(POWER_PARTID_SOR); - unreset_sor_periphs(); + soc_configure_host1x(); /* Now we can write the I2C6 mux in DPAUX */ write32(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL); @@ -106,3 +99,15 @@ void soc_configure_i2c6pad(void) disable_sor_periph_clocks(); clock_set_reset_l(CLK_L_HOST1X); } + +void soc_configure_host1x(void) +{ + power_ungate_partition(POWER_PARTID_SOR); + + /* Host1X needs a valid clock source so DPAUX can be accessed. */ + clock_configure_source(host1x, PLLP, 204000); + + enable_sor_periph_clocks(); + remove_clamps(POWER_PARTID_SOR); + unreset_sor_periphs(); +} |