diff options
Diffstat (limited to 'src/soc/nvidia/tegra132')
| -rw-r--r-- | src/soc/nvidia/tegra132/Kconfig | 9 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/include/soc/memlayout.ld | 7 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld | 9 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/maincpu.S | 55 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/ramstage.c | 12 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/romstage.c | 5 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/stage_entry.S | 24 |
8 files changed, 54 insertions, 68 deletions
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index 8473d4ac5b..04d57835d0 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -17,11 +17,6 @@ config SOC_NVIDIA_TEGRA132 if SOC_NVIDIA_TEGRA132 -# TODO: Remove after replacing arch/arm64/stage_entry.S -config STACK_SIZE - hex - default 0x1000 - config MAINBOARD_DO_DSI_INIT bool "Use dsi graphics interface" depends on MAINBOARD_DO_NATIVE_VGA_INIT @@ -36,10 +31,6 @@ config MAINBOARD_DO_SOR_INIT help Initialize dp display -config MAX_CPUS - int - default 2 - config MTS_DIRECTORY string "Directory where MTS microcode files are located" default "3rdparty/blobs/cpu/nvidia/tegra132/current/prod" diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 22ccba5626..b48fd3ab90 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -90,6 +90,7 @@ ramstage-y += ramstage.c ramstage-y += mmu_operations.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += ../tegra/usb.c +ramstage-y += stage_entry.S modules_arm-y += monotonic_timer.c diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout.ld b/src/soc/nvidia/tegra132/include/soc/memlayout.ld index d403c17127..aad3083132 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout.ld @@ -14,6 +14,7 @@ */ #include <memlayout.h> +#include <rules.h> #include <arch/header.ld> @@ -29,7 +30,11 @@ SECTIONS SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 8K) PRERAM_CBFS_CACHE(0x40002000, 84K) - STACK(0x40017000, 14K) +#if ENV_ARM64 + STACK(0x40017000, 8K) +#else /* AVP gets a separate stack to avoid any chance of handoff races. */ + STACK(0x40019000, 6K) +#endif TIMESTAMP(0x4001A800, 2K) BOOTBLOCK(0x4001B800, 22K) ROMSTAGE(0x40021000, 124K) diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index 7a6a1688fb..e3d221ea75 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -14,6 +14,7 @@ */ #include <memlayout.h> +#include <rules.h> #include <arch/header.ld> @@ -29,8 +30,12 @@ SECTIONS SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 8K) PRERAM_CBFS_CACHE(0x40002000, 72K) - VBOOT2_WORK(0x40014000, 16K) - STACK(0x40018000, 2K) + VBOOT2_WORK(0x40014000, 12K) +#if ENV_ARM64 + STACK(0x40017000, 3K) +#else /* AVP gets a separate stack to avoid any chance of handoff races. */ + STACK(0x40017C00, 3K) +#endif TIMESTAMP(0x40018800, 2K) BOOTBLOCK(0x40019000, 22K) VERSTAGE(0x4001e800, 55K) diff --git a/src/soc/nvidia/tegra132/maincpu.S b/src/soc/nvidia/tegra132/maincpu.S deleted file mode 100644 index 898d821d7e..0000000000 --- a/src/soc/nvidia/tegra132/maincpu.S +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <arch/asm.h> - -ENTRY(maincpu_setup) - /* - * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data - * aborts may happen early and crash before the abort handlers are - * installed, but at least the problem will show up near the code that - * causes it. - */ - msr cpsr, #0xdf - - ldr sp, maincpu_stack_pointer - eor lr, lr - ldr r0, maincpu_entry_point - bx r0 -ENDPROC(maincpu_setup) - - .align 2 - - .global maincpu_stack_pointer -maincpu_stack_pointer: - .word 0 - - .global maincpu_entry_point -maincpu_entry_point: - .word 0 diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c index ca9cec49c3..fec31c4686 100644 --- a/src/soc/nvidia/tegra132/ramstage.c +++ b/src/soc/nvidia/tegra132/ramstage.c @@ -14,6 +14,7 @@ */ #include <arch/stages.h> +#include <gic.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/mc.h> @@ -28,8 +29,14 @@ static void lock_down_vpr(void) write32(®s->video_protect_reg_ctrl, 1); } -void arm64_soc_init(void) +/* Tegra-specific entry point, called from assembly in stage_entry.S */ +void ramstage_entry(void); +void ramstage_entry(void) { + /* TODO: Is this still needed? */ + gic_init(); + + /* TODO: Move TrustZone setup to BL31? */ trustzone_region_init(); tegra132_mmu_init(); @@ -40,4 +47,7 @@ void arm64_soc_init(void) /* Lock down VPR */ lock_down_vpr(); + + /* Jump to boot state machine in common code. */ + main(); } diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index a6753b3a87..3b45aff63d 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -19,6 +19,7 @@ #include <cbmem.h> #include <console/cbmem_console.h> #include <console/console.h> +#include <lib.h> #include <program_loading.h> #include <soc/addressmap.h> #include <soc/ccplex.h> @@ -26,6 +27,7 @@ #include <soc/sdram.h> #include <soc/sdram_configs.h> #include <soc/romstage.h> +#include <symbols.h> #include <timer.h> #include <timestamp.h> @@ -82,6 +84,9 @@ void romstage(void) void platform_prog_run(struct prog *prog) { + /* We'll switch to a new stack, so validate our old one here. */ + checkstack(_estack, 0); + ccplex_cpu_start(prog_entry(prog)); clock_halt_avp(); diff --git a/src/soc/nvidia/tegra132/stage_entry.S b/src/soc/nvidia/tegra132/stage_entry.S new file mode 100644 index 0000000000..de89f9514f --- /dev/null +++ b/src/soc/nvidia/tegra132/stage_entry.S @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/asm.h> + +ENTRY(stage_entry) + /* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */ + bl arm64_init_cpu + + /* Jump to Tegra-specific C entry point. */ + bl ramstage_entry +ENDPROC(stage_entry) |