summaryrefslogtreecommitdiff
path: root/src/soc/nvidia/tegra132
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/nvidia/tegra132')
-rw-r--r--src/soc/nvidia/tegra132/addressmap.c6
-rw-r--r--src/soc/nvidia/tegra132/bootblock.c2
-rw-r--r--src/soc/nvidia/tegra132/ccplex.c14
-rw-r--r--src/soc/nvidia/tegra132/clock.c66
-rw-r--r--src/soc/nvidia/tegra132/cpu.c10
-rw-r--r--src/soc/nvidia/tegra132/dsi.c2
-rw-r--r--src/soc/nvidia/tegra132/flow_ctrl.c2
-rw-r--r--src/soc/nvidia/tegra132/i2c6.c4
-rw-r--r--src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c78
-rw-r--r--src/soc/nvidia/tegra132/padconfig.c14
-rw-r--r--src/soc/nvidia/tegra132/power.c2
-rw-r--r--src/soc/nvidia/tegra132/soc.c6
-rw-r--r--src/soc/nvidia/tegra132/spi.c24
-rw-r--r--src/soc/nvidia/tegra132/uart.c19
14 files changed, 115 insertions, 134 deletions
diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c
index 72563f5095..377d083e02 100644
--- a/src/soc/nvidia/tegra132/addressmap.c
+++ b/src/soc/nvidia/tegra132/addressmap.c
@@ -187,9 +187,9 @@ void trustzone_region_init(void)
return;
/* Set the carveout region. */
- write32(tz_base_mib << 20, &mc->security_cfg0);
- write32(tz_size_mib, &mc->security_cfg1);
+ writel(tz_base_mib << 20, &mc->security_cfg0);
+ writel(tz_size_mib, &mc->security_cfg1);
/* Enable SMMU translations */
- write32(MC_SMMU_CONFIG_ENABLE, &mc->smmu_config);
+ writel(MC_SMMU_CONFIG_ENABLE, &mc->smmu_config);
}
diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c
index ede46ef401..6fd36eb2bd 100644
--- a/src/soc/nvidia/tegra132/bootblock.c
+++ b/src/soc/nvidia/tegra132/bootblock.c
@@ -46,7 +46,7 @@ static void save_odmdata(void)
bct_offset = read32((void *)(TEGRA_SRAM_BASE + BCT_OFFSET_IN_BIT));
if (bct_offset > TEGRA_SRAM_BASE && bct_offset < TEGRA_SRAM_MAX) {
odmdata = read32((void *)(bct_offset + ODMDATA_OFFSET_IN_BCT));
- write32(odmdata, &pmc->odmdata);
+ writel(odmdata, &pmc->odmdata);
}
}
diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c
index 520c244fbf..1cc59add84 100644
--- a/src/soc/nvidia/tegra132/ccplex.c
+++ b/src/soc/nvidia/tegra132/ccplex.c
@@ -46,12 +46,12 @@ static int ccplex_start(void)
struct tegra_pmc_regs * const pmc = PMC_REGS;
/* Set the handshake bit to be knocked down. */
- write32(handshake_mask, &pmc->scratch118);
+ writel(handshake_mask, &pmc->scratch118);
/* Assert nCXRSET[1] */
reg = read32(CLK_RST_REG(rst_cpu_cmplx_set));
reg |= cxreset1_mask;
- write32(reg, CLK_RST_REG(rst_cpu_cmplx_set));
+ writel(reg, CLK_RST_REG(rst_cpu_cmplx_set));
stopwatch_init_msecs_expire(&sw, timeout_ms);
while (1) {
@@ -140,14 +140,14 @@ static void request_ram_repair(void)
/* Perform cluster 0 ram repair */
reg = read32(&flow->ram_repair);
reg |= req;
- write32(reg, &flow->ram_repair);
+ writel(reg, &flow->ram_repair);
while ((read32(&flow->ram_repair) & sts) != sts)
;
/* Perform cluster 1 ram repair */
reg = read32(&flow->ram_repair_cluster1);
reg |= req;
- write32(reg, &flow->ram_repair_cluster1);
+ writel(reg, &flow->ram_repair_cluster1);
while ((read32(&flow->ram_repair_cluster1) & sts) != sts)
;
@@ -169,11 +169,11 @@ void ccplex_cpu_prepare(void)
static void start_common_clocks(void)
{
/* Clear fast CPU partition reset. */
- write32(CRC_RST_CPUG_CLR_NONCPU, CLK_RST_REG(rst_cpug_cmplx_clr));
+ writel(CRC_RST_CPUG_CLR_NONCPU, CLK_RST_REG(rst_cpug_cmplx_clr));
/* Clear reset of L2 and CoreSight components. */
- write32(CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
- CLK_RST_REG(rst_cpug_cmplx_clr));
+ writel(CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
+ CLK_RST_REG(rst_cpug_cmplx_clr));
}
void ccplex_cpu_start(void *entry_addr)
diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c
index 661d38a55d..4cd8a5886d 100644
--- a/src/soc/nvidia/tegra132/clock.c
+++ b/src/soc/nvidia/tegra132/clock.c
@@ -186,11 +186,11 @@ void clock_init_arm_generic_timer(void)
set_cntfrq(freq);
/* Record the system timer frequency. */
- write32(freq, &sysctr->cntfid0);
+ writel(freq, &sysctr->cntfid0);
/* Enable the system counter. */
uint32_t cntcr = read32(&sysctr->cntcr);
cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG;
- write32(cntcr, &sysctr->cntcr);
+ writel(cntcr, &sysctr->cntcr);
}
#define SOR0_CLK_SEL0 (1 << 14)
@@ -243,25 +243,14 @@ static void init_utmip_pll(void)
clrbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */
udelay(1);
- write32(80 << 16 | /* (rst) phy_divn */
- 1 << 8 | /* (rst) phy_divm */
- 0, CLK_RST_REG(utmip_pll_cfg0));/* 960MHz * 1 / 80 == 12 MHz */
+ writel(80 << 16 | 1 << 8 | 0, CLK_RST_REG(utmip_pll_cfg0));/* 960MHz * 1 / 80 == 12 MHz */
- write32(div_round_up(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */
- 0 << 16 | /* PLLU pwrdn */
- 0 << 14 | /* pll_enable pwrdn */
- 0 << 12 | /* pll_active pwrdn */
- div_round_up(khz, 102) << 0 | /* phy_stbl_cnt / 256 (2.5ms) */
- 0, CLK_RST_REG(utmip_pll_cfg1));
+ writel(div_round_up(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | div_round_up(khz, 102) << 0 | 0,
+ CLK_RST_REG(utmip_pll_cfg1));
/* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */
- write32(0 << 24 | /* SAMP_D/XDEV pwrdn */
- div_round_up(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */
- div_round_up(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */
- 0 << 4 | /* SAMP_C/USB3 pwrdn */
- 0 << 2 | /* SAMP_B/XHOST pwrdn */
- 0 << 0 | /* SAMP_A/USBD pwrdn */
- 0, CLK_RST_REG(utmip_pll_cfg2));
+ writel(0 << 24 | div_round_up(khz, 3200) << 18 | div_round_up(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0,
+ CLK_RST_REG(utmip_pll_cfg2));
setbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */
}
@@ -398,9 +387,8 @@ u32 clock_configure_plld(u32 frequency)
* been determined through trial and error (must lead to div 13 at 24MHz). */
void clock_early_uart(void)
{
- write32(CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT |
- CLK_UART_DIV_OVERRIDE |
- CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), CLK_RST_REG(clk_src_uarta));
+ writel(CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900),
+ CLK_RST_REG(clk_src_uarta));
clock_enable_clear_reset_l(CLK_L_UARTA);
}
@@ -503,8 +491,8 @@ void clock_cpu0_config(void)
*/
do {
if (readl(&clst_clk->misc_ctrl) & CLK_SWITCH_MATCH) {
- write32((CC_CCLK_BRST_POL_PLLX_OUT0_LJ << 28),
- &clst_clk->cclk_brst_pol);
+ writel((CC_CCLK_BRST_POL_PLLX_OUT0_LJ << 28),
+ &clst_clk->cclk_brst_pol);
break;
}
@@ -524,9 +512,8 @@ void clock_cpu0_config(void)
void clock_halt_avp(void)
{
for (;;)
- write32(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ |
- FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
- &flow->halt_cop_events);
+ writel(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
+ &flow->halt_cop_events);
}
void clock_init(void)
@@ -542,13 +529,12 @@ void clock_init(void)
/* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA
* features section in the TRM). */
- write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT,
- CLK_RST_REG(clk_sys_rate)); /* pclk = hclk = sclk/2 */
- write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT |
- PLL_OUT_CLKEN | PLL_OUT_RSTN, CLK_RST_REG(pllc_out));
- write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT |
- SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
- CLK_RST_REG(sclk_brst_pol)); /* sclk = 300 MHz */
+ writel(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT,
+ CLK_RST_REG(clk_sys_rate)); /* pclk = hclk = sclk/2 */
+ writel(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN,
+ CLK_RST_REG(pllc_out));
+ writel(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
+ CLK_RST_REG(sclk_brst_pol)); /* sclk = 300 MHz */
/* Change the oscillator drive strength (from U-Boot -- why?) */
clrsetbits_le32(CLK_RST_REG(osc_ctrl), OSC_XOFS_MASK,
@@ -563,16 +549,10 @@ void clock_init(void)
OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT);
/* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */
- write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT |
- PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT |
- (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT |
- PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT,
- CLK_RST_REG(pllp_outa));
- write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT |
- PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT |
- (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT |
- PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
- CLK_RST_REG(pllp_outb));
+ writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT,
+ CLK_RST_REG(pllp_outa));
+ writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
+ CLK_RST_REG(pllp_outb));
/* init pllu */
init_pll(CLK_RST_REG(pllu_base), CLK_RST_REG(pllu_misc),
diff --git a/src/soc/nvidia/tegra132/cpu.c b/src/soc/nvidia/tegra132/cpu.c
index c79bc9cf4e..8cd2c0faea 100644
--- a/src/soc/nvidia/tegra132/cpu.c
+++ b/src/soc/nvidia/tegra132/cpu.c
@@ -40,15 +40,15 @@ static void enable_core_clocks(int cpu)
/* Clear reset of CPU components. */
if (cpu == 0)
- write32(cpu0_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
+ writel(cpu0_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
else
- write32(cpu1_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
+ writel(cpu1_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
}
static void set_armv8_32bit_reset_vector(uintptr_t entry)
{
void * const evp_cpu_reset_vector = EVP_CPU_RESET_VECTOR;
- write32(entry, evp_cpu_reset_vector);
+ writel(entry, evp_cpu_reset_vector);
}
static void set_armv8_64bit_reset_vector(uintptr_t entry)
@@ -56,8 +56,8 @@ static void set_armv8_64bit_reset_vector(uintptr_t entry)
struct tegra_pmc_regs * const pmc = PMC_REGS;
/* Currently assume 32-bit addresses only. */
- write32(entry, &pmc->secure_scratch34);
- write32(0, &pmc->secure_scratch35);
+ writel(entry, &pmc->secure_scratch34);
+ writel(0, &pmc->secure_scratch35);
}
void cpu_prepare_startup(void *entry_64)
diff --git a/src/soc/nvidia/tegra132/dsi.c b/src/soc/nvidia/tegra132/dsi.c
index 188792bd2c..8508b6666d 100644
--- a/src/soc/nvidia/tegra132/dsi.c
+++ b/src/soc/nvidia/tegra132/dsi.c
@@ -869,7 +869,7 @@ static int dsi_enable(struct soc_nvidia_tegra132_config *config)
tegra_output_dsi_setup_clock(dsi_a, config);
/* configure APB_MISC_GP_MIPI_PAD_CTRL_0 */
- write32(DSIB_MODE_DSI, (unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0);
+ writel(DSIB_MODE_DSI, (unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0);
/* configure phy interface timing registers */
tegra_dsi_set_phy_timing(dsi_a);
diff --git a/src/soc/nvidia/tegra132/flow_ctrl.c b/src/soc/nvidia/tegra132/flow_ctrl.c
index 4da54b1ea1..6d7d11590c 100644
--- a/src/soc/nvidia/tegra132/flow_ctrl.c
+++ b/src/soc/nvidia/tegra132/flow_ctrl.c
@@ -62,7 +62,7 @@ static uint32_t flowctrl_read_cpu_csr(int cpu)
static void flowctrl_write_cpu_csr(int cpu, uint32_t val)
{
- write32(val, tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
+ writel(val, tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
val = readl(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
}
diff --git a/src/soc/nvidia/tegra132/i2c6.c b/src/soc/nvidia/tegra132/i2c6.c
index 73a98562ad..ef86126935 100644
--- a/src/soc/nvidia/tegra132/i2c6.c
+++ b/src/soc/nvidia/tegra132/i2c6.c
@@ -43,7 +43,7 @@ static void remove_clamps(int id)
return;
/* Remove clamp */
- write32((1 << id), &pmc->remove_clamping_cmd);
+ writel((1 << id), &pmc->remove_clamping_cmd);
/* Wait for clamp off */
while (partition_clamp_on(id))
@@ -86,7 +86,7 @@ void soc_configure_i2c6pad(void)
soc_configure_host1x();
/* Now we can write the I2C6 mux in DPAUX */
- write32(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);
+ writel(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);
/*
* Delay before turning off Host1X/DPAUX clocks.
diff --git a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
index a52e918ee0..29fb9dedd6 100644
--- a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
@@ -261,17 +261,17 @@ inline static void write32(uint32_t val, void *addr)
inline static void setbits32(uint32_t bits, void *addr)
{
- write32(read32(addr) | bits, addr);
+ writel(read32(addr) | bits, addr);
}
inline static void clrbits32(uint32_t bits, void *addr)
{
- write32(read32(addr) & ~bits, addr);
+ writel(read32(addr) & ~bits, addr);
}
static void __attribute__((noreturn)) reset(void)
{
- write32(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr);
+ writel(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr);
halt();
}
@@ -370,18 +370,18 @@ static void enable_uart(void)
clrbits32(uart_mask, uart_rst_reg);
/* Program UART clock source: PLLP (408000000) */
- write32(0, uart_clk_source);
+ writel(0, uart_clk_source);
/* Program 115200n8 to the uart port */
/* baud-rate of 115200 */
- write32(LCR_DLAB, (uart_base + UART_LCR));
- write32((UART_RATE_115200 & 0xff), (uart_base + UART_THR_DLAB));
- write32((UART_RATE_115200 >> 8), (uart_base + UART_IER_DLAB));
+ writel(LCR_DLAB, (uart_base + UART_LCR));
+ writel((UART_RATE_115200 & 0xff), (uart_base + UART_THR_DLAB));
+ writel((UART_RATE_115200 >> 8), (uart_base + UART_IER_DLAB));
/* 8-bit and no parity */
- write32(LCR_WD_SIZE_8, (uart_base + UART_LCR));
+ writel(LCR_WD_SIZE_8, (uart_base + UART_LCR));
/* enable and clear RX/TX FIFO */
- write32((FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO),
- (uart_base + UART_IIR_FCR));
+ writel((FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO),
+ (uart_base + UART_IIR_FCR));
}
/* Accessors. */
@@ -401,7 +401,7 @@ static unsigned get_osc_freq(void)
static void enable_jtag(void)
{
- write32(PP_CONFIG_CTL_JTAG, misc_pp_config_ctl_ptr);
+ writel(PP_CONFIG_CTL_JTAG, misc_pp_config_ctl_ptr);
}
/* Clock configuration. */
@@ -417,7 +417,7 @@ static void config_oscillator(void)
osc_ctrl &= ~OSC_XOFS_MASK;
osc_ctrl |= (xofs << OSC_XOFS_SHIFT);
osc_ctrl |= OSC_XOE;
- write32(osc_ctrl, clk_rst_osc_ctrl_ptr);
+ writel(osc_ctrl, clk_rst_osc_ctrl_ptr);
}
static void config_pllu(void)
@@ -462,24 +462,24 @@ static void config_pllu(void)
// Configure PLLU.
uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE |
(divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT);
- write32(base, clk_rst_pllu_base_ptr);
+ writel(base, clk_rst_pllu_base_ptr);
uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) |
(lfcon << PLLU_LFCON_SHIFT);
- write32(misc, clk_rst_pllu_misc_ptr);
+ writel(misc, clk_rst_pllu_misc_ptr);
// Enable PLLU.
base &= ~PLLU_BYPASS;
base |= PLLU_ENABLE;
- write32(base, clk_rst_pllu_base_ptr);
+ writel(base, clk_rst_pllu_base_ptr);
misc |= PLLU_LOCK_ENABLE;
- write32(misc, clk_rst_pllu_misc_ptr);
+ writel(misc, clk_rst_pllu_misc_ptr);
}
static void enable_cpu_clocks(void)
{
// Enable the CPU complex clock.
- write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
- write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
+ writel(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
+ writel(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
}
@@ -489,7 +489,7 @@ static void enable_cpu_clocks(void)
static void config_core_sight(void)
{
// Enable the CoreSight clock.
- write32(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr);
+ writel(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr);
/*
* De-assert CoreSight reset.
@@ -497,7 +497,7 @@ static void config_core_sight(void)
* now. It will be restored to its original clock source
* when the CPU-side restoration code runs.
*/
- write32(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr);
+ writel(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr);
}
@@ -508,11 +508,11 @@ static void clear_cpu_resets(void)
/* Hold CPU1 in reset */
setbits32(SET_CXRESET1, clk_rst_rst_cpulp_cmplx_set_ptr);
- write32(CLR_NONCPURESET | CLR_L2RESET | CLR_PRESETDBG,
- clk_rst_rst_cpug_cmplx_clr_ptr);
+ writel(CLR_NONCPURESET | CLR_L2RESET | CLR_PRESETDBG,
+ clk_rst_rst_cpug_cmplx_clr_ptr);
- write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0,
- clk_rst_rst_cpug_cmplx_clr_ptr);
+ writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0,
+ clk_rst_rst_cpug_cmplx_clr_ptr);
}
@@ -542,7 +542,7 @@ static void power_on_partition(unsigned id)
uint32_t bit = 0x1 << id;
if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) {
// Partition is not on. Turn it on.
- write32(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr);
+ writel(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr);
// Wait until the partition is powerd on.
while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit))
@@ -572,15 +572,15 @@ static void power_on_main_cpu(void)
*/
uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr);
- write32(orig_timer * (204000000 / 32768),
- pmc_ctlr_cpupwrgood_timer_ptr);
+ writel(orig_timer * (204000000 / 32768),
+ pmc_ctlr_cpupwrgood_timer_ptr);
power_on_partition(PARTID_CRAIL);
power_on_partition(PARTID_C0NC);
power_on_partition(PARTID_CE0);
// Restore the original PMC_CPUPWRGOOD_TIMER.
- write32(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
+ writel(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
}
@@ -609,7 +609,7 @@ void lp0_resume(void)
config_oscillator();
// Program SUPER_CCLK_DIVIDER.
- write32(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr);
+ writel(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr);
config_core_sight();
@@ -623,12 +623,12 @@ void lp0_resume(void)
* T132 always resets to AARCH32 and SW needs to write RMR_EL3
* to bootstrap into AARCH64.
*/
- write32(get_wakeup_vector(), pmc_ctlr_secure_scratch34_ptr);
- write32(0, pmc_ctlr_secure_scratch35_ptr);
- write32((uint32_t)aarch64_trampoline, evp_cpu_reset_ptr);
+ writel(get_wakeup_vector(), pmc_ctlr_secure_scratch34_ptr);
+ writel(0, pmc_ctlr_secure_scratch35_ptr);
+ writel((uint32_t)aarch64_trampoline, evp_cpu_reset_ptr);
// Select CPU complex clock source.
- write32(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr);
+ writel(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr);
// Disable PLLX since it isn't used as CPU clock source.
clrbits32(PLLX_ENABLE, clk_rst_pllx_base_ptr);
@@ -637,12 +637,12 @@ void lp0_resume(void)
uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr);
ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK;
ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT;
- write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
+ writel(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
// Disable VPR.
- write32(0, mc_video_protect_size_mb_ptr);
- write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
- mc_video_protect_reg_ctrl_ptr);
+ writel(0, mc_video_protect_size_mb_ptr);
+ writel(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
+ mc_video_protect_reg_ctrl_ptr);
enable_cpu_clocks();
@@ -655,8 +655,8 @@ void lp0_resume(void)
// Halt the AVP.
while (1)
- write32(FLOW_MODE_STOP | EVENT_JTAG,
- flow_ctlr_halt_cop_events_ptr);
+ writel(FLOW_MODE_STOP | EVENT_JTAG,
+ flow_ctlr_halt_cop_events_ptr);
}
diff --git a/src/soc/nvidia/tegra132/padconfig.c b/src/soc/nvidia/tegra132/padconfig.c
index 5f7f2e4f93..790f10f9c0 100644
--- a/src/soc/nvidia/tegra132/padconfig.c
+++ b/src/soc/nvidia/tegra132/padconfig.c
@@ -36,7 +36,7 @@ static inline uint32_t pad_get_pinmux(int index)
static inline void pad_set_pinmux(int index, uint32_t reg)
{
- return write32(reg, &pinmux_regs[index]);
+ return writel(reg, &pinmux_regs[index]);
}
static inline void pad_set_gpio_out(int gpio_index, int val)
@@ -45,10 +45,10 @@ static inline void pad_set_gpio_out(int gpio_index, int val)
int port = gpio_index_to_port(gpio_index);
int bit = gpio_to_bit(gpio_index);
- write32((1 << (bit + GPIO_GPIOS_PER_PORT)) | (val << bit),
- &regs->out_value_mask[port]);
- write32((1 << (bit + GPIO_GPIOS_PER_PORT)) | (1 << bit),
- &regs->out_enable_mask[port]);
+ writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (val << bit),
+ &regs->out_value_mask[port]);
+ writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (1 << bit),
+ &regs->out_enable_mask[port]);
}
static inline void pad_set_mode(int gpio_index, int sfio_or_gpio)
@@ -57,8 +57,8 @@ static inline void pad_set_mode(int gpio_index, int sfio_or_gpio)
int port = gpio_index_to_port(gpio_index);
int bit = gpio_to_bit(gpio_index);
- write32((1 << (bit + GPIO_GPIOS_PER_PORT)) | (sfio_or_gpio << bit),
- &regs->config_mask[port]);
+ writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (sfio_or_gpio << bit),
+ &regs->config_mask[port]);
}
static inline void pad_set_gpio_mode(int gpio_index)
diff --git a/src/soc/nvidia/tegra132/power.c b/src/soc/nvidia/tegra132/power.c
index 4316d763db..0ebfd7c53e 100644
--- a/src/soc/nvidia/tegra132/power.c
+++ b/src/soc/nvidia/tegra132/power.c
@@ -41,7 +41,7 @@ void power_ungate_partition(uint32_t id)
pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK);
pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT);
pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START;
- write32(pwrgate_toggle, &pmc->pwrgate_toggle);
+ writel(pwrgate_toggle, &pmc->pwrgate_toggle);
/* Wait for the request to be accepted. */
while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START)
diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c
index 476dec7a03..7923f7e3cd 100644
--- a/src/soc/nvidia/tegra132/soc.c
+++ b/src/soc/nvidia/tegra132/soc.c
@@ -83,9 +83,9 @@ static void lock_down_vpr(void)
{
struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE;
- write32(0, &regs->video_protect_bom);
- write32(0, &regs->video_protect_size_mb);
- write32(1, &regs->video_protect_reg_ctrl);
+ writel(0, &regs->video_protect_bom);
+ writel(0, &regs->video_protect_size_mb);
+ writel(1, &regs->video_protect_reg_ctrl);
}
static void soc_init(device_t dev)
diff --git a/src/soc/nvidia/tegra132/spi.c b/src/soc/nvidia/tegra132/spi.c
index 0bff31a245..e240700f06 100644
--- a/src/soc/nvidia/tegra132/spi.c
+++ b/src/soc/nvidia/tegra132/spi.c
@@ -230,7 +230,7 @@ int spi_claim_bus(struct spi_slave *slave)
else
val |= SPI_CMD1_CS_SW_VAL;
- write32(val, &regs->command1);
+ writel(val, &regs->command1);
return 0;
}
@@ -246,7 +246,7 @@ void spi_release_bus(struct spi_slave *slave)
else
val &= ~SPI_CMD1_CS_SW_VAL;
- write32(val, &regs->command1);
+ writel(val, &regs->command1);
}
static void dump_fifo_status(struct tegra_spi_channel *spi)
@@ -383,12 +383,12 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi,
/* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and
* PIO transfers */
- write32(todo - 1, &spi->regs->dma_blk);
+ writel(todo - 1, &spi->regs->dma_blk);
if (dir == SPI_SEND) {
unsigned int to_fifo = bytes;
while (to_fifo) {
- write32(*p, &spi->regs->tx_fifo);
+ writel(*p, &spi->regs->tx_fifo);
p++;
to_fifo--;
}
@@ -493,11 +493,12 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
/* ensure bytes to send will be visible to DMA controller */
dcache_clean_by_mva(spi->out_buf, bytes);
- write32((uintptr_t)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr);
- write32((uintptr_t)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
+ writel((uintptr_t) & spi->regs->tx_fifo,
+ &spi->dma_out->regs->apb_ptr);
+ writel((uintptr_t)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR);
setup_dma_params(spi, spi->dma_out);
- write32(wcount, &spi->dma_out->regs->wcount);
+ writel(wcount, &spi->dma_out->regs->wcount);
} else {
spi->dma_in = dma_claim();
if (!spi->dma_in)
@@ -506,15 +507,16 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
/* avoid data collisions */
dcache_clean_invalidate_by_mva(spi->in_buf, bytes);
- write32((uintptr_t)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr);
- write32((uintptr_t)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
+ writel((uintptr_t)&spi->regs->rx_fifo,
+ &spi->dma_in->regs->apb_ptr);
+ writel((uintptr_t)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR);
setup_dma_params(spi, spi->dma_in);
- write32(wcount, &spi->dma_in->regs->wcount);
+ writel(wcount, &spi->dma_in->regs->wcount);
}
/* BLOCK_SIZE starts at n-1 */
- write32(todo - 1, &spi->regs->dma_blk);
+ writel(todo - 1, &spi->regs->dma_blk);
return todo;
}
diff --git a/src/soc/nvidia/tegra132/uart.c b/src/soc/nvidia/tegra132/uart.c
index 3a9ac22584..90765e1496 100644
--- a/src/soc/nvidia/tegra132/uart.c
+++ b/src/soc/nvidia/tegra132/uart.c
@@ -63,20 +63,19 @@ static void tegra132_uart_init(struct tegra132_uart *uart_ptr)
tegra132_uart_tx_flush(uart_ptr);
// Disable interrupts.
- write8(0, &uart_ptr->ier);
+ writeb(0, &uart_ptr->ier);
// Force DTR and RTS to high.
- write8(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
+ writeb(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
// Set line configuration, access divisor latches.
- write8(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
+ writeb(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
// Set the divisor.
- write8(divisor & 0xff, &uart_ptr->dll);
- write8((divisor >> 8) & 0xff, &uart_ptr->dlm);
+ writeb(divisor & 0xff, &uart_ptr->dll);
+ writeb((divisor >> 8) & 0xff, &uart_ptr->dlm);
// Hide the divisor latches.
- write8(line_config, &uart_ptr->lcr);
+ writeb(line_config, &uart_ptr->lcr);
// Enable FIFOs, and clear receive and transmit.
- write8(UART8250_FCR_FIFO_EN |
- UART8250_FCR_CLEAR_RCVR |
- UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr);
+ writeb(UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT,
+ &uart_ptr->fcr);
}
static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr)
@@ -89,7 +88,7 @@ static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr)
static void tegra132_uart_tx_byte(struct tegra132_uart *uart_ptr, unsigned char data)
{
while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE));
- write8(data, &uart_ptr->thr);
+ writeb(data, &uart_ptr->thr);
}
static void tegra132_uart_tx_flush(struct tegra132_uart *uart_ptr)
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 11:39:46 +0000