diff options
Diffstat (limited to 'src/soc/nvidia')
30 files changed, 862 insertions, 850 deletions
diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c index 292d21d02f..3f7df5bd0e 100644 --- a/src/soc/nvidia/tegra/apbmisc.c +++ b/src/soc/nvidia/tegra/apbmisc.c @@ -26,12 +26,12 @@ static struct apbmisc *misc = (struct apbmisc *)TEGRA_APB_MISC_BASE; void enable_jtag(void) { - writel(PP_CONFIG_CTL_JTAG, &misc->pp_config_ctl); + write32(&misc->pp_config_ctl, PP_CONFIG_CTL_JTAG); } void clamp_tristate_inputs(void) { - writel(PP_PINMUX_CLAMP_INPUTS, &misc->pp_pinmux_global); + write32(&misc->pp_pinmux_global, PP_PINMUX_CLAMP_INPUTS); } void tegra_revision_info(struct tegra_revision *id) diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c index 8179580add..e0561c057d 100644 --- a/src/soc/nvidia/tegra/gpio.c +++ b/src/soc/nvidia/tegra/gpio.c @@ -67,8 +67,8 @@ static void gpio_write_port(int index, size_t offset, u32 mask, u32 value) u32 new_reg = (reg & ~mask) | (value & mask); if (new_reg != reg) { - writel(new_reg, - (u8 *)&gpio_banks[bank] + offset + port * sizeof(u32)); + write32((u8 *)&gpio_banks[bank] + offset + port * sizeof(u32), + new_reg); } } diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index b9a5f42a37..1d5df3c342 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -40,9 +40,9 @@ static void do_bus_clear(int bus) // 4. Set TERMINATE condition (1 = IMMEDIATE) bc = read32(®s->bus_clear_config); bc |= I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE; - writel(bc, ®s->bus_clear_config); + write32(®s->bus_clear_config, bc); // 4.1 Set MSTR_CONFIG_LOAD and wait for clear - writel(I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE, ®s->config_load); + write32(®s->config_load, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE); for (i = 0; i < timeout_ms * 10 && (read32(®s->config_load) & I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE); i++) { printk(BIOS_DEBUG, "%s: wait for MSTR_CONFIG_LOAD to clear\n", @@ -50,7 +50,7 @@ static void do_bus_clear(int bus) udelay(100); } // 5. Set ENABLE to start the bus clear op - writel(bc | I2C_BUS_CLEAR_CONFIG_BC_ENABLE, ®s->bus_clear_config); + write32(®s->bus_clear_config, bc | I2C_BUS_CLEAR_CONFIG_BC_ENABLE); for (i = 0; i < timeout_ms * 10 && (read32(®s->bus_clear_config) & I2C_BUS_CLEAR_CONFIG_BC_ENABLE); i++) { printk(BIOS_DEBUG, "%s: wait for bus clear completion\n", @@ -74,7 +74,7 @@ static int tegra_i2c_send_recv(int bus, int read, rx_full >>= I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT; while (header_words && tx_empty) { - writel(*headers++, ®s->tx_packet_fifo); + write32(®s->tx_packet_fifo, *headers++); header_words--; tx_empty--; } @@ -96,7 +96,7 @@ static int tegra_i2c_send_recv(int bus, int read, int todo = MIN(data_len, sizeof(word)); memcpy(&word, data, todo); - writel(word, ®s->tx_packet_fifo); + write32(®s->tx_packet_fifo, word); data_len -= todo; data += sizeof(word); tx_empty--; @@ -208,5 +208,5 @@ void i2c_init(unsigned bus) { struct tegra_i2c_regs * const regs = tegra_i2c_info[bus].base; - writel(I2C_CNFG_PACKET_MODE_EN, ®s->cnfg); + write32(®s->cnfg, I2C_CNFG_PACKET_MODE_EN); } diff --git a/src/soc/nvidia/tegra/pingroup.c b/src/soc/nvidia/tegra/pingroup.c index c856c173ac..332e05aeaa 100644 --- a/src/soc/nvidia/tegra/pingroup.c +++ b/src/soc/nvidia/tegra/pingroup.c @@ -26,7 +26,7 @@ static uint32_t *pingroup_regs = (void *)TEGRA_APB_PINGROUP_BASE; void pingroup_set_config(int group_index, uint32_t config) { - writel(config, &pingroup_regs[group_index]); + write32(&pingroup_regs[group_index], config); } uint32_t pingroup_get_config(int group_index) diff --git a/src/soc/nvidia/tegra/pinmux.c b/src/soc/nvidia/tegra/pinmux.c index a88a063cac..f28b0266e7 100644 --- a/src/soc/nvidia/tegra/pinmux.c +++ b/src/soc/nvidia/tegra/pinmux.c @@ -26,7 +26,7 @@ static uint32_t *pinmux_regs = (void *)TEGRA_APB_PINMUX_BASE; void pinmux_set_config(int pin_index, uint32_t config) { - writel(config, &pinmux_regs[pin_index]); + write32(&pinmux_regs[pin_index], config); } uint32_t pinmux_get_config(int pin_index) diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c index c666c40f3b..4a069fa02e 100644 --- a/src/soc/nvidia/tegra/usb.c +++ b/src/soc/nvidia/tegra/usb.c @@ -126,7 +126,7 @@ static void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type t { int timeout = 1000; - writel(1 << 1, &usb->ehci_usbcmd); /* Host Controller Reset */ + write32(&usb->ehci_usbcmd, 1 << 1); /* Host Controller Reset */ /* TODO: Resets are long, find way to parallelize... or just use XHCI */ while (--timeout && (read32(&usb->ehci_usbcmd) & 1 << 1)) /* wait for HC to reset */; @@ -137,11 +137,11 @@ static void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type t } /* Controller mode: HOST */ - writel(3 << 0, &usb->usb_mode); + write32(&usb->usb_mode, 3 << 0); /* Parallel transceiver selct */ - writel(type << 29, &usb->lpm_ctrl); + write32(&usb->lpm_ctrl, type << 29); /* Tx FIFO Burst thresh */ - writel(0x10 << 16, &usb->tx_fill_tuning); + write32(&usb->tx_fill_tuning, 0x10 << 16); } /* Assume USBx clocked, out of reset, UTMI+ PLL set up, SAMP_x out of pwrdn */ @@ -157,27 +157,27 @@ void usb_setup_utmip(void *usb_base) udelay(1); /* Take stuff out of pwrdn and add some magic numbers from U-Boot */ - writel(0x8 << 25 | 0x3 << 22 | 0 << 21 | 0 << 18 | 0 << 16 | 0 << 14 | 1 << 13 | 0x1 << 10 | 0x1 << 8 | 0x4 << 0 | 0, - &usb->utmip.xcvr0); - writel(0x7 << 18 | 0 << 4 | 0 << 2 | 0 << 0 | 0, &usb->utmip.xcvr1); - writel(1 << 19 | 1 << 16 | 1 << 9 | 0, &usb->utmip.tx); - writel(0x2 << 30 | 1 << 28 | 0x1 << 24 | 0x3 << 21 | 0x11 << 15 | 0x10 << 10 | 0, - &usb->utmip.hsrx0); + write32(&usb->utmip.xcvr0, + 0x8 << 25 | 0x3 << 22 | 0 << 21 | 0 << 18 | 0 << 16 | 0 << 14 | 1 << 13 | 0x1 << 10 | 0x1 << 8 | 0x4 << 0 | 0); + write32(&usb->utmip.xcvr1, 0x7 << 18 | 0 << 4 | 0 << 2 | 0 << 0 | 0); + write32(&usb->utmip.tx, 1 << 19 | 1 << 16 | 1 << 9 | 0); + write32(&usb->utmip.hsrx0, + 0x2 << 30 | 1 << 28 | 0x1 << 24 | 0x3 << 21 | 0x11 << 15 | 0x10 << 10 | 0); /* U-Boot claims the USBD values for these are used across all UTMI+ * PHYs. That sounds so horribly wrong that I'm not going to implement * it, but keep it in mind if we're ever not using the USBD port. */ - writel(0x1 << 24 | 1 << 23 | 1 << 22 | 1 << 11 | 0 << 10 | 0x1 << 2 | 0x2 << 0 | 0, - &usb->utmip.bias0); + write32(&usb->utmip.bias0, + 0x1 << 24 | 1 << 23 | 1 << 22 | 1 << 11 | 0 << 10 | 0x1 << 2 | 0x2 << 0 | 0); - writel(khz / 2200 << 3 | 1 << 2 | 0 << 0 | 0, &usb->utmip.bias1); + write32(&usb->utmip.bias1, khz / 2200 << 3 | 1 << 2 | 0 << 0 | 0); - writel(0xffff << 16 | 25 * khz / 10 << 0 | 0, &usb->utmip.debounce); + write32(&usb->utmip.debounce, 0xffff << 16 | 25 * khz / 10 << 0 | 0); udelay(1); setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ - writel(1 << 12 | 0 << 11 | 0, &usb->suspend_ctrl); + write32(&usb->suspend_ctrl, 1 << 12 | 0 << 11 | 0); usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP); printk(BIOS_DEBUG, "USB controller @ %p set up with UTMI+ PHY\n",usb_base); diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index dc1d1dbe8a..1d124b220f 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -163,7 +163,7 @@ struct { */ static u32 clock_get_osc_bits(void) { - return (readl(&clk_rst->osc_ctrl) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; + return (read32(&clk_rst->osc_ctrl) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; } int clock_get_osc_khz(void) @@ -173,7 +173,7 @@ int clock_get_osc_khz(void) int clock_get_pll_input_khz(void) { - u32 osc_ctrl = readl(&clk_rst->osc_ctrl); + u32 osc_ctrl = read32(&clk_rst->osc_ctrl); u32 osc_bits = (osc_ctrl & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; u32 pll_ref_div = (osc_ctrl & OSC_PREDIV_MASK) >> OSC_PREDIV_SHIFT; return osc_table[osc_bits].khz >> pll_ref_div; @@ -186,11 +186,11 @@ void clock_init_arm_generic_timer(void) set_cntfrq(freq); // Record the system timer frequency. - writel(freq, &sysctr->cntfid0); + write32(&sysctr->cntfid0, freq); // Enable the system counter. uint32_t cntcr = read32(&sysctr->cntcr); cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG; - writel(cntcr, &sysctr->cntcr); + write32(&sysctr->cntcr, cntcr); } #define SOR0_CLK_SEL0 (1 << 14) @@ -221,18 +221,18 @@ static void init_pll(u32 *base, u32 *misc, const union pll_fields pll, u32 lock) pll.div.lfcon << PLL_MISC_LFCON_SHIFT; /* Write dividers but BYPASS the PLL while we're messing with it. */ - writel(dividers | PLL_BASE_BYPASS, base); + write32(base, dividers | PLL_BASE_BYPASS); /* * Set Lock bit, CPCON and LFCON fields (default to 0 if it doesn't * exist for this PLL) */ - writel(lock | misc_con, misc); + write32(misc, lock | misc_con); /* Enable PLL and take it back out of BYPASS */ - writel(dividers | PLL_BASE_ENABLE, base); + write32(base, dividers | PLL_BASE_ENABLE); /* Wait for lock ready */ - while (!(readl(base) & PLL_BASE_LOCK)); + while (!(read32(base) & PLL_BASE_LOCK)); } static void init_utmip_pll(void) @@ -243,14 +243,14 @@ static void init_utmip_pll(void) clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ udelay(1); - writel(80 << 16 | 1 << 8 | 0, &clk_rst->utmip_pll_cfg0); /* 960MHz * 1 / 80 == 12 MHz */ + write32(&clk_rst->utmip_pll_cfg0, 80 << 16 | 1 << 8 | 0); /* 960MHz * 1 / 80 == 12 MHz */ - writel(CEIL_DIV(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | CEIL_DIV(khz, 102) << 0 | 0, - &clk_rst->utmip_pll_cfg1); + write32(&clk_rst->utmip_pll_cfg1, + CEIL_DIV(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | CEIL_DIV(khz, 102) << 0 | 0); /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ - writel(0 << 24 | CEIL_DIV(khz, 3200) << 18 | CEIL_DIV(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0, - &clk_rst->utmip_pll_cfg2); + write32(&clk_rst->utmip_pll_cfg2, + 0 << 24 | CEIL_DIV(khz, 3200) << 18 | CEIL_DIV(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0); setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ } @@ -274,12 +274,12 @@ static void graphics_pll(void) * that it is needed. */ u32 scfg = (1<<28) | (1<<24) | (1<<22); - writel(scfg, cfg); + write32(cfg, scfg); init_pll(&clk_rst->plldp_base, &clk_rst->plldp_misc, osc_table[osc].plldp, PLLDPD2_MISC_LOCK_ENABLE); /* leave dither and undoc bits set, release clamp */ scfg = (1<<28) | (1<<24); - writel(scfg, cfg); + write32(cfg, scfg); /* disp1 will be set when panel information (pixel clock) is * retrieved (clock_display). @@ -387,8 +387,8 @@ clock_display(u32 frequency) * been determined through trial and error (must lead to div 13 at 24MHz). */ void clock_early_uart(void) { - writel(CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), - &clk_rst->clk_src_uarta); + write32(&clk_rst->clk_src_uarta, + CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900)); setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA); udelay(2); clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA); @@ -438,22 +438,22 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, * values after coldboot reset). */ - writel(misc1, &clk_rst->pllm_misc1); - writel(misc2, &clk_rst->pllm_misc2); + write32(&clk_rst->pllm_misc1, misc1); + write32(&clk_rst->pllm_misc2, misc2); /* PLLM.BASE needs BYPASS=0, different from general init_pll */ - base = readl(&clk_rst->pllm_base); + base = read32(&clk_rst->pllm_base); base &= ~(PLLCMX_BASE_DIVN_MASK | PLLCMX_BASE_DIVM_MASK | PLLM_BASE_DIVP_MASK | PLL_BASE_BYPASS); base |= ((m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) | (p << PLL_BASE_DIVP_SHIFT)); - writel(base, &clk_rst->pllm_base); + write32(&clk_rst->pllm_base, base); setbits_le32(&clk_rst->pllm_base, PLL_BASE_ENABLE); /* stable_time is required, before we can start to check lock. */ udelay(stable_time); - while (!(readl(&clk_rst->pllm_base) & PLL_BASE_LOCK)) { + while (!(read32(&clk_rst->pllm_base) & PLL_BASE_LOCK)) { udelay(1); } /* @@ -467,7 +467,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, /* Enable and start MEM(MC) and EMC. */ clock_enable_clear_reset(0, CLK_H_MEM | CLK_H_EMC, 0, 0, 0, 0); - writel(emc_source, &clk_rst->clk_src_emc); + write32(&clk_rst->clk_src_emc, emc_source); udelay(IO_STABILIZATION_DELAY); } @@ -475,24 +475,24 @@ void clock_cpu0_config(void *entry) { void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; - writel((uintptr_t)_estack, &maincpu_stack_pointer); - writel((uintptr_t)entry, &maincpu_entry_point); - writel((uintptr_t)&maincpu_setup, evp_cpu_reset); + write32(&maincpu_stack_pointer, (uintptr_t)_estack); + write32(&maincpu_entry_point, (uintptr_t)entry); + write32(evp_cpu_reset, (uintptr_t)&maincpu_setup); /* Set active CPU cluster to G */ clrbits_le32(&flow->cluster_control, 1); // Set up cclk_brst and divider. - writel((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28), - &clk_rst->cclk_brst_pol); - writel(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB, - &clk_rst->super_cclk_div); + write32(&clk_rst->cclk_brst_pol, + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28)); + write32(&clk_rst->super_cclk_div, + CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB); // Enable the clocks for CPUs 0-3. uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr); cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP | CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP; - writel(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr); + write32(&clk_rst->clk_cpu_cmplx_clr, cpu_cmplx_clr); // Enable other CPU related clocks. setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); @@ -503,23 +503,23 @@ void clock_cpu0_config(void *entry) void clock_cpu0_remove_reset(void) { // Disable the reset on the non-CPU parts of the fast cluster. - writel(CRC_RST_CPUG_CLR_NONCPU, &clk_rst->rst_cpug_cmplx_clr); + write32(&clk_rst->rst_cpug_cmplx_clr, CRC_RST_CPUG_CLR_NONCPU); // Disable the various resets on the CPUs. - writel(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG, - &clk_rst->rst_cpug_cmplx_clr); + write32(&clk_rst->rst_cpug_cmplx_clr, + CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG); // Disable the reset on the non-CPU parts of the slow cluster. - writel(CRC_RST_CPULP_CLR_NONCPU, &clk_rst->rst_cpulp_cmplx_clr); + write32(&clk_rst->rst_cpulp_cmplx_clr, CRC_RST_CPULP_CLR_NONCPU); // Disable the various resets on the LP CPU. - writel(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG, - &clk_rst->rst_cpulp_cmplx_clr); + write32(&clk_rst->rst_cpulp_cmplx_clr, + CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG); } void clock_halt_avp(void) { for (;;) { - writel(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT, - &flow->halt_cop_events); + write32(&flow->halt_cop_events, + FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT); } } @@ -528,7 +528,7 @@ void clock_init(void) u32 osc = clock_get_osc_bits(); /* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */ - writel(0x2b << 17 | 0xb << 9, &clk_rst->pllc_misc2); + write32(&clk_rst->pllc_misc2, 0x2b << 17 | 0xb << 9); /* Max out the AVP clock before everything else (need PLLC for that). */ init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc, @@ -536,12 +536,12 @@ void clock_init(void) /* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA * features section in the TRM). */ - writel(TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT | TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT, - &clk_rst->clk_sys_rate); - writel(CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN, - &clk_rst->pllc_out); - writel(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT, - &clk_rst->sclk_brst_pol); /* sclk = 300 MHz */ + write32(&clk_rst->clk_sys_rate, + TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT | TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT); + write32(&clk_rst->pllc_out, + CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN); + write32(&clk_rst->sclk_brst_pol, + SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* sclk = 300 MHz */ /* Change the oscillator drive strength (from U-Boot -- why?) */ clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK, @@ -559,10 +559,10 @@ void clock_init(void) clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK); /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ - writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT, - &clk_rst->pllp_outa); - writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT, - &clk_rst->pllp_outb); + write32(&clk_rst->pllp_outa, + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT); + write32(&clk_rst->pllp_outb, + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT); /* init pllx */ init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, @@ -578,62 +578,62 @@ void clock_init(void) void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) { - if (l) writel(l, &clk_rst->clk_enb_l_set); - if (h) writel(h, &clk_rst->clk_enb_h_set); - if (u) writel(u, &clk_rst->clk_enb_u_set); - if (v) writel(v, &clk_rst->clk_enb_v_set); - if (w) writel(w, &clk_rst->clk_enb_w_set); - if (x) writel(x, &clk_rst->clk_enb_x_set); + if (l) write32(&clk_rst->clk_enb_l_set, l); + if (h) write32(&clk_rst->clk_enb_h_set, h); + if (u) write32(&clk_rst->clk_enb_u_set, u); + if (v) write32(&clk_rst->clk_enb_v_set, v); + if (w) write32(&clk_rst->clk_enb_w_set, w); + if (x) write32(&clk_rst->clk_enb_x_set, x); /* Give clocks time to stabilize. */ udelay(IO_STABILIZATION_DELAY); - if (l) writel(l, &clk_rst->rst_dev_l_clr); - if (h) writel(h, &clk_rst->rst_dev_h_clr); - if (u) writel(u, &clk_rst->rst_dev_u_clr); - if (v) writel(v, &clk_rst->rst_dev_v_clr); - if (w) writel(w, &clk_rst->rst_dev_w_clr); - if (x) writel(x, &clk_rst->rst_dev_x_clr); + if (l) write32(&clk_rst->rst_dev_l_clr, l); + if (h) write32(&clk_rst->rst_dev_h_clr, h); + if (u) write32(&clk_rst->rst_dev_u_clr, u); + if (v) write32(&clk_rst->rst_dev_v_clr, v); + if (w) write32(&clk_rst->rst_dev_w_clr, w); + if (x) write32(&clk_rst->rst_dev_x_clr, x); } void clock_reset_l(u32 bit) { - writel(bit, &clk_rst->rst_dev_l_set); + write32(&clk_rst->rst_dev_l_set, bit); udelay(1); - writel(bit, &clk_rst->rst_dev_l_clr); + write32(&clk_rst->rst_dev_l_clr, bit); } void clock_reset_h(u32 bit) { - writel(bit, &clk_rst->rst_dev_h_set); + write32(&clk_rst->rst_dev_h_set, bit); udelay(1); - writel(bit, &clk_rst->rst_dev_h_clr); + write32(&clk_rst->rst_dev_h_clr, bit); } void clock_reset_u(u32 bit) { - writel(bit, &clk_rst->rst_dev_u_set); + write32(&clk_rst->rst_dev_u_set, bit); udelay(1); - writel(bit, &clk_rst->rst_dev_u_clr); + write32(&clk_rst->rst_dev_u_clr, bit); } void clock_reset_v(u32 bit) { - writel(bit, &clk_rst->rst_dev_v_set); + write32(&clk_rst->rst_dev_v_set, bit); udelay(1); - writel(bit, &clk_rst->rst_dev_v_clr); + write32(&clk_rst->rst_dev_v_clr, bit); } void clock_reset_w(u32 bit) { - writel(bit, &clk_rst->rst_dev_w_set); + write32(&clk_rst->rst_dev_w_set, bit); udelay(1); - writel(bit, &clk_rst->rst_dev_w_clr); + write32(&clk_rst->rst_dev_w_clr, bit); } void clock_reset_x(u32 bit) { - writel(bit, &clk_rst->rst_dev_x_set); + write32(&clk_rst->rst_dev_x_set, bit); udelay(1); - writel(bit, &clk_rst->rst_dev_x_clr); + write32(&clk_rst->rst_dev_x_clr, bit); } diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 71fff1c93e..7273090eec 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -53,7 +53,7 @@ unsigned long READL(void * p) if (dump > 1) printk(BIOS_SPEW, "readl %p\n", p); - value = readl(p); + value = read32(p); if (dump) printk(BIOS_SPEW, "readl %p %08lx\n", p, value); return value; @@ -63,7 +63,7 @@ void WRITEL(unsigned long value, void * p) { if (dump) printk(BIOS_SPEW, "writel %p %08lx\n", p, value); - writel(value, p); + write32(p, value); } /* return in 1000ths of a Hertz */ diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 9418e152da..2ed2103d15 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -282,17 +282,17 @@ inline static void write32(uint32_t val, void *addr) inline static void setbits32(uint32_t bits, void *addr) { - writel(read32(addr) | bits, addr); + write32(addr, read32(addr) | bits); } inline static void clrbits32(uint32_t bits, void *addr) { - writel(read32(addr) & ~bits, addr); + write32(addr, read32(addr) & ~bits); } static void __attribute__((noreturn)) reset(void) { - writel(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr); + write32(clk_rst_rst_devices_l_ptr, SWR_TRIG_SYS_RST); halt(); } @@ -337,7 +337,7 @@ static void config_oscillator(void) osc_ctrl &= ~OSC_XOFS_MASK; osc_ctrl |= (xofs << OSC_XOFS_SHIFT); osc_ctrl |= OSC_XOE; - writel(osc_ctrl, clk_rst_osc_ctrl_ptr); + write32(clk_rst_osc_ctrl_ptr, osc_ctrl); } static void config_pllu(void) @@ -382,17 +382,17 @@ static void config_pllu(void) // Configure PLLU. uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE | (divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT); - writel(base, clk_rst_pllu_base_ptr); + write32(clk_rst_pllu_base_ptr, base); uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) | (lfcon << PLLU_LFCON_SHIFT); - writel(misc, clk_rst_pllu_misc_ptr); + write32(clk_rst_pllu_misc_ptr, misc); // Enable PLLU. base &= ~PLLU_BYPASS; base |= PLLU_ENABLE; - writel(base, clk_rst_pllu_base_ptr); + write32(clk_rst_pllu_base_ptr, base); misc |= PLLU_LOCK_ENABLE; - writel(misc, clk_rst_pllu_misc_ptr); + write32(clk_rst_pllu_misc_ptr, misc); } static void config_tsc(void) @@ -400,26 +400,26 @@ static void config_tsc(void) // Tell the TSC the oscillator frequency. switch (get_osc_freq()) { case OSC_FREQ_12: - writel(12000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 12000000); break; case OSC_FREQ_48: - writel(48000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 48000000); break; case OSC_FREQ_16P8: - writel(16800000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 16800000); break; case OSC_FREQ_19P2: - writel(19200000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 19200000); break; case OSC_FREQ_38P4: - writel(38400000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 38400000); break; case OSC_FREQ_26: - writel(26000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 26000000); break; default: // Default to 13MHz. - writel(13000000, sysctr_cntfid0_ptr); + write32(sysctr_cntfid0_ptr, 13000000); break; } @@ -430,8 +430,8 @@ static void config_tsc(void) static void enable_cpu_clocks(void) { // Enable the CPU complex clock. - writel(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr); - writel(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr); + write32(clk_rst_clk_enb_l_set_ptr, CLK_ENB_CPU); + write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP); } @@ -441,7 +441,7 @@ static void enable_cpu_clocks(void) static void config_core_sight(void) { // Enable the CoreSight clock. - writel(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr); + write32(clk_rst_clk_out_enb_u_set_ptr, CLK_ENB_CSITE); /* * De-assert CoreSight reset. @@ -449,22 +449,22 @@ static void config_core_sight(void) * now. It will be restored to its original clock source * when the CPU-side restoration code runs. */ - writel(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr); + write32(clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST); } static void config_mselect(void) { // Set MSELECT clock source to PLLP with 1:4 divider. - writel((6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0, - clk_rst_clk_src_mselect_ptr); + write32(clk_rst_clk_src_mselect_ptr, + (6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0); // Enable clock to MSELECT. - writel(CLK_ENB_MSELECT, clk_rst_clk_enb_v_set_ptr); + write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_MSELECT); udelay(2); // Bring MSELECT out of reset. - writel(SWR_MSELECT_RST, clk_rst_rst_dev_v_clr_ptr); + write32(clk_rst_rst_dev_v_clr_ptr, SWR_MSELECT_RST); } @@ -474,16 +474,16 @@ static void config_mselect(void) static void clear_cpu_resets(void) { // Take the non-cpu of the G and LP clusters out of reset. - writel(CLR_NONCPURESET, clk_rst_rst_cpulp_cmplx_clr_ptr); - writel(CLR_NONCPURESET, clk_rst_rst_cpug_cmplx_clr_ptr); + write32(clk_rst_rst_cpulp_cmplx_clr_ptr, CLR_NONCPURESET); + write32(clk_rst_rst_cpug_cmplx_clr_ptr, CLR_NONCPURESET); // Clear software controlled reset of the slow cluster. - writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0, - clk_rst_rst_cpulp_cmplx_clr_ptr); + write32(clk_rst_rst_cpulp_cmplx_clr_ptr, + CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0); // Clear software controlled reset of the fast cluster. - writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3, - clk_rst_rst_cpug_cmplx_clr_ptr); + write32(clk_rst_rst_cpug_cmplx_clr_ptr, + CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3); } @@ -513,7 +513,8 @@ static void power_on_partition(unsigned id) uint32_t bit = 0x1 << id; if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) { // Partition is not on. Turn it on. - writel(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr); + write32(pmc_ctlr_pwrgate_toggle_ptr, + id | PWRGATE_TOGGLE_START); // Wait until the partition is powerd on. while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) @@ -543,8 +544,8 @@ static void power_on_main_cpu(void) */ uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr); - writel(orig_timer * (204000000 / 32768), - pmc_ctlr_cpupwrgood_timer_ptr); + write32(pmc_ctlr_cpupwrgood_timer_ptr, + orig_timer * (204000000 / 32768)); if (wakeup_on_lp()) { power_on_partition(PARTID_C1NC); @@ -556,7 +557,7 @@ static void power_on_main_cpu(void) } // Restore the original PMC_CPUPWRGOOD_TIMER. - writel(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr); + write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer); } @@ -578,17 +579,17 @@ void lp0_resume(void) flow_ctlr_cluster_control_ptr); // Program SUPER_CCLK_DIVIDER. - writel(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr); + write32(clk_rst_super_cclk_div_ptr, SUPER_CDIV_ENB); config_core_sight(); config_pllu(); // Set the CPU reset vector. - writel(get_wakeup_vector(), evp_cpu_reset_ptr); + write32(evp_cpu_reset_ptr, get_wakeup_vector()); // Select CPU complex clock source. - writel(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr); + write32(clk_rst_cclk_burst_policy_ptr, CCLK_PLLP_BURST_POLICY); config_mselect(); @@ -599,14 +600,14 @@ void lp0_resume(void) uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr); ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK; ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT; - writel(ack_width, clk_rst_cpu_softrst_ctrl2_ptr); + write32(clk_rst_cpu_softrst_ctrl2_ptr, ack_width); config_tsc(); // Disable VPR. - writel(0, mc_video_protect_size_mb_ptr); - writel(VIDEO_PROTECT_WRITE_ACCESS_DISABLE, - mc_video_protect_reg_ctrl_ptr); + write32(mc_video_protect_size_mb_ptr, 0); + write32(mc_video_protect_reg_ctrl_ptr, + VIDEO_PROTECT_WRITE_ACCESS_DISABLE); enable_cpu_clocks(); @@ -619,8 +620,8 @@ void lp0_resume(void) // Halt the AVP. while (1) - writel(FLOW_MODE_STOP | EVENT_JTAG, - flow_ctlr_halt_cop_events_ptr); + write32(flow_ctlr_halt_cop_events_ptr, + FLOW_MODE_STOP | EVENT_JTAG); } diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c index b31d3a7781..962a8e12e3 100644 --- a/src/soc/nvidia/tegra124/power.c +++ b/src/soc/nvidia/tegra124/power.c @@ -48,7 +48,7 @@ static void power_ungate_partition(uint32_t id) pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK); pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT); pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START; - writel(pwrgate_toggle, &pmc->pwrgate_toggle); + write32(&pmc->pwrgate_toggle, pwrgate_toggle); // Wait for the request to be accepted. while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START) @@ -73,12 +73,12 @@ void power_enable_and_ungate_cpu(void) * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (150MHz), * set it for 5ms as per SysEng (5ms * PCLK_KHZ * 1000 / 1s). */ - writel((TEGRA_PCLK_KHZ * 5), &pmc->cpupwrgood_timer); + write32(&pmc->cpupwrgood_timer, (TEGRA_PCLK_KHZ * 5)); uint32_t cntrl = read32(&pmc->cntrl); cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY; cntrl |= PMC_CNTRL_CPUPWRREQ_OE; - writel(cntrl, &pmc->cntrl); + write32(&pmc->cntrl, cntrl); power_ungate_partition(POWER_PARTID_CRAIL); diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index d094c18594..dc6fd92544 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -33,7 +33,7 @@ static void sdram_patch(uintptr_t addr, uint32_t value) { if (addr) - writel(value, (uint32_t*)addr); + write32((uint32_t *)addr, value); } static void writebits(uint32_t value, uint32_t *addr, uint32_t mask) @@ -46,7 +46,7 @@ static void sdram_configure_pmc(const struct sdram_params *param, struct tegra_pmc_regs *regs) { /* VDDP Select */ - writel(param->PmcVddpSel, ®s->vddp_sel); + write32(®s->vddp_sel, param->PmcVddpSel); udelay(param->PmcVddpSelWait); /* Set DDR pad voltage */ @@ -62,7 +62,7 @@ static void sdram_configure_pmc(const struct sdram_params *param, writebits(param->PmcNoIoPower, ®s->no_iopower, (PMC_NO_IOPOWER_MEM_MASK | PMC_NO_IOPOWER_MEM_COMP_MASK)); - writel(param->PmcRegShort, ®s->reg_short); + write32(®s->reg_short, param->PmcRegShort); } static void sdram_start_clocks(const struct sdram_params *param) @@ -102,148 +102,151 @@ static void sdram_deassert_sel_dpd(const struct sdram_params *param, static void sdram_set_swizzle(const struct sdram_params *param, struct tegra_emc_regs *regs) { - writel(param->EmcSwizzleRank0ByteCfg, ®s->swizzle_rank0_byte_cfg); - writel(param->EmcSwizzleRank0Byte0, ®s->swizzle_rank0_byte0); - writel(param->EmcSwizzleRank0Byte1, ®s->swizzle_rank0_byte1); - writel(param->EmcSwizzleRank0Byte2, ®s->swizzle_rank0_byte2); - writel(param->EmcSwizzleRank0Byte3, ®s->swizzle_rank0_byte3); - writel(param->EmcSwizzleRank1ByteCfg, ®s->swizzle_rank1_byte_cfg); - writel(param->EmcSwizzleRank1Byte0, ®s->swizzle_rank1_byte0); - writel(param->EmcSwizzleRank1Byte1, ®s->swizzle_rank1_byte1); - writel(param->EmcSwizzleRank1Byte2, ®s->swizzle_rank1_byte2); - writel(param->EmcSwizzleRank1Byte3, ®s->swizzle_rank1_byte3); + write32(®s->swizzle_rank0_byte_cfg, param->EmcSwizzleRank0ByteCfg); + write32(®s->swizzle_rank0_byte0, param->EmcSwizzleRank0Byte0); + write32(®s->swizzle_rank0_byte1, param->EmcSwizzleRank0Byte1); + write32(®s->swizzle_rank0_byte2, param->EmcSwizzleRank0Byte2); + write32(®s->swizzle_rank0_byte3, param->EmcSwizzleRank0Byte3); + write32(®s->swizzle_rank1_byte_cfg, param->EmcSwizzleRank1ByteCfg); + write32(®s->swizzle_rank1_byte0, param->EmcSwizzleRank1Byte0); + write32(®s->swizzle_rank1_byte1, param->EmcSwizzleRank1Byte1); + write32(®s->swizzle_rank1_byte2, param->EmcSwizzleRank1Byte2); + write32(®s->swizzle_rank1_byte3, param->EmcSwizzleRank1Byte3); } static void sdram_set_pad_controls(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program the pad controls */ - writel(param->EmcXm2CmdPadCtrl, ®s->xm2cmdpadctrl); - writel(param->EmcXm2CmdPadCtrl2, ®s->xm2cmdpadctrl2); - writel(param->EmcXm2CmdPadCtrl3, ®s->xm2cmdpadctrl3); - writel(param->EmcXm2CmdPadCtrl4, ®s->xm2cmdpadctrl4); - writel(param->EmcXm2CmdPadCtrl5, ®s->xm2cmdpadctrl5); + write32(®s->xm2cmdpadctrl, param->EmcXm2CmdPadCtrl); + write32(®s->xm2cmdpadctrl2, param->EmcXm2CmdPadCtrl2); + write32(®s->xm2cmdpadctrl3, param->EmcXm2CmdPadCtrl3); + write32(®s->xm2cmdpadctrl4, param->EmcXm2CmdPadCtrl4); + write32(®s->xm2cmdpadctrl5, param->EmcXm2CmdPadCtrl5); - writel(param->EmcXm2DqsPadCtrl, ®s->xm2dqspadctrl); - writel(param->EmcXm2DqsPadCtrl2, ®s->xm2dqspadctrl2); - writel(param->EmcXm2DqsPadCtrl3, ®s->xm2dqspadctrl3); - writel(param->EmcXm2DqsPadCtrl4, ®s->xm2dqspadctrl4); - writel(param->EmcXm2DqsPadCtrl5, ®s->xm2dqspadctrl5); - writel(param->EmcXm2DqsPadCtrl6, ®s->xm2dqspadctrl6); + write32(®s->xm2dqspadctrl, param->EmcXm2DqsPadCtrl); + write32(®s->xm2dqspadctrl2, param->EmcXm2DqsPadCtrl2); + write32(®s->xm2dqspadctrl3, param->EmcXm2DqsPadCtrl3); + write32(®s->xm2dqspadctrl4, param->EmcXm2DqsPadCtrl4); + write32(®s->xm2dqspadctrl5, param->EmcXm2DqsPadCtrl5); + write32(®s->xm2dqspadctrl6, param->EmcXm2DqsPadCtrl6); - writel(param->EmcXm2DqPadCtrl, ®s->xm2dqpadctrl); - writel(param->EmcXm2DqPadCtrl2, ®s->xm2dqpadctrl2); - writel(param->EmcXm2DqPadCtrl3, ®s->xm2dqpadctrl3); + write32(®s->xm2dqpadctrl, param->EmcXm2DqPadCtrl); + write32(®s->xm2dqpadctrl2, param->EmcXm2DqPadCtrl2); + write32(®s->xm2dqpadctrl3, param->EmcXm2DqPadCtrl3); - writel(param->EmcXm2ClkPadCtrl, ®s->xm2clkpadctrl); - writel(param->EmcXm2ClkPadCtrl2, ®s->xm2clkpadctrl2); + write32(®s->xm2clkpadctrl, param->EmcXm2ClkPadCtrl); + write32(®s->xm2clkpadctrl2, param->EmcXm2ClkPadCtrl2); - writel(param->EmcXm2CompPadCtrl, ®s->xm2comppadctrl); + write32(®s->xm2comppadctrl, param->EmcXm2CompPadCtrl); - writel(param->EmcXm2VttGenPadCtrl, ®s->xm2vttgenpadctrl); - writel(param->EmcXm2VttGenPadCtrl2, ®s->xm2vttgenpadctrl2); - writel(param->EmcXm2VttGenPadCtrl3, ®s->xm2vttgenpadctrl3); + write32(®s->xm2vttgenpadctrl, param->EmcXm2VttGenPadCtrl); + write32(®s->xm2vttgenpadctrl2, param->EmcXm2VttGenPadCtrl2); + write32(®s->xm2vttgenpadctrl3, param->EmcXm2VttGenPadCtrl3); - writel(param->EmcCttTermCtrl, ®s->ctt_term_ctrl); + write32(®s->ctt_term_ctrl, param->EmcCttTermCtrl); } static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs) { - writel(EMC_TIMING_CONTROL_TIMING_UPDATE, ®s->timing_control); + write32(®s->timing_control, EMC_TIMING_CONTROL_TIMING_UPDATE); } static void sdram_init_mc(const struct sdram_params *param, struct tegra_mc_regs *regs) { /* Initialize MC VPR settings */ - writel(param->McDisplaySnapRing, ®s->display_snap_ring); - writel(param->McVideoProtectBom, ®s->video_protect_bom); - writel(param->McVideoProtectBomAdrHi, ®s->video_protect_bom_adr_hi); - writel(param->McVideoProtectSizeMb, ®s->video_protect_size_mb); - writel(param->McVideoProtectVprOverride, - ®s->video_protect_vpr_override); - writel(param->McVideoProtectVprOverride1, - ®s->video_protect_vpr_override1); - writel(param->McVideoProtectGpuOverride0, - ®s->video_protect_gpu_override_0); - writel(param->McVideoProtectGpuOverride1, - ®s->video_protect_gpu_override_1); + write32(®s->display_snap_ring, param->McDisplaySnapRing); + write32(®s->video_protect_bom, param->McVideoProtectBom); + write32(®s->video_protect_bom_adr_hi, + param->McVideoProtectBomAdrHi); + write32(®s->video_protect_size_mb, param->McVideoProtectSizeMb); + write32(®s->video_protect_vpr_override, + param->McVideoProtectVprOverride); + write32(®s->video_protect_vpr_override1, + param->McVideoProtectVprOverride1); + write32(®s->video_protect_gpu_override_0, + param->McVideoProtectGpuOverride0); + write32(®s->video_protect_gpu_override_1, + param->McVideoProtectGpuOverride1); /* Program SDRAM geometry paarameters */ - writel(param->McEmemAdrCfg, ®s->emem_adr_cfg); - writel(param->McEmemAdrCfgDev0, ®s->emem_adr_cfg_dev0); - writel(param->McEmemAdrCfgDev1, ®s->emem_adr_cfg_dev1); + write32(®s->emem_adr_cfg, param->McEmemAdrCfg); + write32(®s->emem_adr_cfg_dev0, param->McEmemAdrCfgDev0); + write32(®s->emem_adr_cfg_dev1, param->McEmemAdrCfgDev1); /* Program bank swizzling */ - writel(param->McEmemAdrCfgBankMask0, ®s->emem_bank_swizzle_cfg0); - writel(param->McEmemAdrCfgBankMask1, ®s->emem_bank_swizzle_cfg1); - writel(param->McEmemAdrCfgBankMask2, ®s->emem_bank_swizzle_cfg2); - writel(param->McEmemAdrCfgBankSwizzle3, ®s->emem_bank_swizzle_cfg3); + write32(®s->emem_bank_swizzle_cfg0, param->McEmemAdrCfgBankMask0); + write32(®s->emem_bank_swizzle_cfg1, param->McEmemAdrCfgBankMask1); + write32(®s->emem_bank_swizzle_cfg2, param->McEmemAdrCfgBankMask2); + write32(®s->emem_bank_swizzle_cfg3, + param->McEmemAdrCfgBankSwizzle3); /* Program external memory aperature (base and size) */ - writel(param->McEmemCfg, ®s->emem_cfg); + write32(®s->emem_cfg, param->McEmemCfg); /* Program SEC carveout (base and size) */ - writel(param->McSecCarveoutBom, ®s->sec_carveout_bom); - writel(param->McSecCarveoutAdrHi, ®s->sec_carveout_adr_hi); - writel(param->McSecCarveoutSizeMb, ®s->sec_carveout_size_mb); + write32(®s->sec_carveout_bom, param->McSecCarveoutBom); + write32(®s->sec_carveout_adr_hi, param->McSecCarveoutAdrHi); + write32(®s->sec_carveout_size_mb, param->McSecCarveoutSizeMb); /* Program MTS carveout (base and size) */ - writel(param->McMtsCarveoutBom, ®s->mts_carveout_bom); - writel(param->McMtsCarveoutAdrHi, ®s->mts_carveout_adr_hi); - writel(param->McMtsCarveoutSizeMb, ®s->mts_carveout_size_mb); + write32(®s->mts_carveout_bom, param->McMtsCarveoutBom); + write32(®s->mts_carveout_adr_hi, param->McMtsCarveoutAdrHi); + write32(®s->mts_carveout_size_mb, param->McMtsCarveoutSizeMb); /* Program the memory arbiter */ - writel(param->McEmemArbCfg, ®s->emem_arb_cfg); - writel(param->McEmemArbOutstandingReq, ®s->emem_arb_outstanding_req); - writel(param->McEmemArbTimingRcd, ®s->emem_arb_timing_rcd); - writel(param->McEmemArbTimingRp, ®s->emem_arb_timing_rp); - writel(param->McEmemArbTimingRc, ®s->emem_arb_timing_rc); - writel(param->McEmemArbTimingRas, ®s->emem_arb_timing_ras); - writel(param->McEmemArbTimingFaw, ®s->emem_arb_timing_faw); - writel(param->McEmemArbTimingRrd, ®s->emem_arb_timing_rrd); - writel(param->McEmemArbTimingRap2Pre, ®s->emem_arb_timing_rap2pre); - writel(param->McEmemArbTimingWap2Pre, ®s->emem_arb_timing_wap2pre); - writel(param->McEmemArbTimingR2R, ®s->emem_arb_timing_r2r); - writel(param->McEmemArbTimingW2W, ®s->emem_arb_timing_w2w); - writel(param->McEmemArbTimingR2W, ®s->emem_arb_timing_r2w); - writel(param->McEmemArbTimingW2R, ®s->emem_arb_timing_w2r); - writel(param->McEmemArbDaTurns, ®s->emem_arb_da_turns); - writel(param->McEmemArbDaCovers, ®s->emem_arb_da_covers); - writel(param->McEmemArbMisc0, ®s->emem_arb_misc0); - writel(param->McEmemArbMisc1, ®s->emem_arb_misc1); - writel(param->McEmemArbRing1Throttle, ®s->emem_arb_ring1_throttle); - writel(param->McEmemArbOverride, ®s->emem_arb_override); - writel(param->McEmemArbOverride1, ®s->emem_arb_override_1); - writel(param->McEmemArbRsv, ®s->emem_arb_rsv); + write32(®s->emem_arb_cfg, param->McEmemArbCfg); + write32(®s->emem_arb_outstanding_req, + param->McEmemArbOutstandingReq); + write32(®s->emem_arb_timing_rcd, param->McEmemArbTimingRcd); + write32(®s->emem_arb_timing_rp, param->McEmemArbTimingRp); + write32(®s->emem_arb_timing_rc, param->McEmemArbTimingRc); + write32(®s->emem_arb_timing_ras, param->McEmemArbTimingRas); + write32(®s->emem_arb_timing_faw, param->McEmemArbTimingFaw); + write32(®s->emem_arb_timing_rrd, param->McEmemArbTimingRrd); + write32(®s->emem_arb_timing_rap2pre, param->McEmemArbTimingRap2Pre); + write32(®s->emem_arb_timing_wap2pre, param->McEmemArbTimingWap2Pre); + write32(®s->emem_arb_timing_r2r, param->McEmemArbTimingR2R); + write32(®s->emem_arb_timing_w2w, param->McEmemArbTimingW2W); + write32(®s->emem_arb_timing_r2w, param->McEmemArbTimingR2W); + write32(®s->emem_arb_timing_w2r, param->McEmemArbTimingW2R); + write32(®s->emem_arb_da_turns, param->McEmemArbDaTurns); + write32(®s->emem_arb_da_covers, param->McEmemArbDaCovers); + write32(®s->emem_arb_misc0, param->McEmemArbMisc0); + write32(®s->emem_arb_misc1, param->McEmemArbMisc1); + write32(®s->emem_arb_ring1_throttle, param->McEmemArbRing1Throttle); + write32(®s->emem_arb_override, param->McEmemArbOverride); + write32(®s->emem_arb_override_1, param->McEmemArbOverride1); + write32(®s->emem_arb_rsv, param->McEmemArbRsv); /* Program extra snap levels for display client */ - writel(param->McDisExtraSnapLevels, ®s->dis_extra_snap_levels); + write32(®s->dis_extra_snap_levels, param->McDisExtraSnapLevels); /* Trigger MC timing update */ - writel(MC_TIMING_CONTROL_TIMING_UPDATE, ®s->timing_control); + write32(®s->timing_control, MC_TIMING_CONTROL_TIMING_UPDATE); /* Program second-level clock enable overrides */ - writel(param->McClkenOverride, ®s->clken_override); + write32(®s->clken_override, param->McClkenOverride); /* Program statistics gathering */ - writel(param->McStatControl, ®s->stat_control); + write32(®s->stat_control, param->McStatControl); } static void sdram_init_emc(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program SDRAM geometry parameters */ - writel(param->EmcAdrCfg, ®s->adr_cfg); + write32(®s->adr_cfg, param->EmcAdrCfg); /* Program second-level clock enable overrides */ - writel(param->EmcClkenOverride, ®s->clken_override); + write32(®s->clken_override, param->EmcClkenOverride); /* Program EMC pad auto calibration */ - writel(param->EmcAutoCalInterval, ®s->auto_cal_interval); - writel(param->EmcAutoCalConfig2, ®s->auto_cal_config2); - writel(param->EmcAutoCalConfig3, ®s->auto_cal_config3); - writel(param->EmcAutoCalConfig, ®s->auto_cal_config); + write32(®s->auto_cal_interval, param->EmcAutoCalInterval); + write32(®s->auto_cal_config2, param->EmcAutoCalConfig2); + write32(®s->auto_cal_config3, param->EmcAutoCalConfig3); + write32(®s->auto_cal_config, param->EmcAutoCalConfig); udelay(param->EmcAutoCalWait); } @@ -251,129 +254,129 @@ static void sdram_set_emc_timing(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program EMC timing configuration */ - writel(param->EmcCfg2, ®s->cfg_2); - writel(param->EmcCfgPipe, ®s->cfg_pipe); - writel(param->EmcDbg, ®s->dbg); - writel(param->EmcCmdQ, ®s->cmdq); - writel(param->EmcMc2EmcQ, ®s->mc2emcq); - writel(param->EmcMrsWaitCnt, ®s->mrs_wait_cnt); - writel(param->EmcMrsWaitCnt2, ®s->mrs_wait_cnt2); - writel(param->EmcFbioCfg5, ®s->fbio_cfg5); - writel(param->EmcRc, ®s->rc); - writel(param->EmcRfc, ®s->rfc); - writel(param->EmcRfcSlr, ®s->rfc_slr); - writel(param->EmcRas, ®s->ras); - writel(param->EmcRp, ®s->rp); - writel(param->EmcR2r, ®s->r2r); - writel(param->EmcW2w, ®s->w2w); - writel(param->EmcR2w, ®s->r2w); - writel(param->EmcW2r, ®s->w2r); - writel(param->EmcR2p, ®s->r2p); - writel(param->EmcW2p, ®s->w2p); - writel(param->EmcRdRcd, ®s->rd_rcd); - writel(param->EmcWrRcd, ®s->wr_rcd); - writel(param->EmcRrd, ®s->rrd); - writel(param->EmcRext, ®s->rext); - writel(param->EmcWext, ®s->wext); - writel(param->EmcWdv, ®s->wdv); - writel(param->EmcWdvMask, ®s->wdv_mask); - writel(param->EmcQUse, ®s->quse); - writel(param->EmcQuseWidth, ®s->quse_width); - writel(param->EmcIbdly, ®s->ibdly); - writel(param->EmcEInput, ®s->einput); - writel(param->EmcEInputDuration, ®s->einput_duration); - writel(param->EmcPutermExtra, ®s->puterm_extra); - writel(param->EmcPutermWidth, ®s->puterm_width); - writel(param->EmcPutermAdj, ®s->puterm_adj); - writel(param->EmcCdbCntl1, ®s->cdb_cntl_1); - writel(param->EmcCdbCntl2, ®s->cdb_cntl_2); - writel(param->EmcCdbCntl3, ®s->cdb_cntl_3); - writel(param->EmcQRst, ®s->qrst); - writel(param->EmcQSafe, ®s->qsafe); - writel(param->EmcRdv, ®s->rdv); - writel(param->EmcRdvMask, ®s->rdv_mask); - writel(param->EmcQpop, ®s->qpop); - writel(param->EmcCtt, ®s->ctt); - writel(param->EmcCttDuration, ®s->ctt_duration); - writel(param->EmcRefresh, ®s->refresh); - writel(param->EmcBurstRefreshNum, ®s->burst_refresh_num); - writel(param->EmcPreRefreshReqCnt, ®s->pre_refresh_req_cnt); - writel(param->EmcPdEx2Wr, ®s->pdex2wr); - writel(param->EmcPdEx2Rd, ®s->pdex2rd); - writel(param->EmcPChg2Pden, ®s->pchg2pden); - writel(param->EmcAct2Pden, ®s->act2pden); - writel(param->EmcAr2Pden, ®s->ar2pden); - writel(param->EmcRw2Pden, ®s->rw2pden); - writel(param->EmcTxsr, ®s->txsr); - writel(param->EmcTxsrDll, ®s->txsrdll); - writel(param->EmcTcke, ®s->tcke); - writel(param->EmcTckesr, ®s->tckesr); - writel(param->EmcTpd, ®s->tpd); - writel(param->EmcTfaw, ®s->tfaw); - writel(param->EmcTrpab, ®s->trpab); - writel(param->EmcTClkStable, ®s->tclkstable); - writel(param->EmcTClkStop, ®s->tclkstop); - writel(param->EmcTRefBw, ®s->trefbw); - writel(param->EmcOdtWrite, ®s->odt_write); - writel(param->EmcOdtRead, ®s->odt_read); - writel(param->EmcFbioCfg6, ®s->fbio_cfg6); - writel(param->EmcCfgDigDll, ®s->cfg_dig_dll); - writel(param->EmcCfgDigDllPeriod, ®s->cfg_dig_dll_period); + write32(®s->cfg_2, param->EmcCfg2); + write32(®s->cfg_pipe, param->EmcCfgPipe); + write32(®s->dbg, param->EmcDbg); + write32(®s->cmdq, param->EmcCmdQ); + write32(®s->mc2emcq, param->EmcMc2EmcQ); + write32(®s->mrs_wait_cnt, param->EmcMrsWaitCnt); + write32(®s->mrs_wait_cnt2, param->EmcMrsWaitCnt2); + write32(®s->fbio_cfg5, param->EmcFbioCfg5); + write32(®s->rc, param->EmcRc); + write32(®s->rfc, param->EmcRfc); + write32(®s->rfc_slr, param->EmcRfcSlr); + write32(®s->ras, param->EmcRas); + write32(®s->rp, param->EmcRp); + write32(®s->r2r, param->EmcR2r); + write32(®s->w2w, param->EmcW2w); + write32(®s->r2w, param->EmcR2w); + write32(®s->w2r, param->EmcW2r); + write32(®s->r2p, param->EmcR2p); + write32(®s->w2p, param->EmcW2p); + write32(®s->rd_rcd, param->EmcRdRcd); + write32(®s->wr_rcd, param->EmcWrRcd); + write32(®s->rrd, param->EmcRrd); + write32(®s->rext, param->EmcRext); + write32(®s->wext, param->EmcWext); + write32(®s->wdv, param->EmcWdv); + write32(®s->wdv_mask, param->EmcWdvMask); + write32(®s->quse, param->EmcQUse); + write32(®s->quse_width, param->EmcQuseWidth); + write32(®s->ibdly, param->EmcIbdly); + write32(®s->einput, param->EmcEInput); + write32(®s->einput_duration, param->EmcEInputDuration); + write32(®s->puterm_extra, param->EmcPutermExtra); + write32(®s->puterm_width, param->EmcPutermWidth); + write32(®s->puterm_adj, param->EmcPutermAdj); + write32(®s->cdb_cntl_1, param->EmcCdbCntl1); + write32(®s->cdb_cntl_2, param->EmcCdbCntl2); + write32(®s->cdb_cntl_3, param->EmcCdbCntl3); + write32(®s->qrst, param->EmcQRst); + write32(®s->qsafe, param->EmcQSafe); + write32(®s->rdv, param->EmcRdv); + write32(®s->rdv_mask, param->EmcRdvMask); + write32(®s->qpop, param->EmcQpop); + write32(®s->ctt, param->EmcCtt); + write32(®s->ctt_duration, param->EmcCttDuration); + write32(®s->refresh, param->EmcRefresh); + write32(®s->burst_refresh_num, param->EmcBurstRefreshNum); + write32(®s->pre_refresh_req_cnt, param->EmcPreRefreshReqCnt); + write32(®s->pdex2wr, param->EmcPdEx2Wr); + write32(®s->pdex2rd, param->EmcPdEx2Rd); + write32(®s->pchg2pden, param->EmcPChg2Pden); + write32(®s->act2pden, param->EmcAct2Pden); + write32(®s->ar2pden, param->EmcAr2Pden); + write32(®s->rw2pden, param->EmcRw2Pden); + write32(®s->txsr, param->EmcTxsr); + write32(®s->txsrdll, param->EmcTxsrDll); + write32(®s->tcke, param->EmcTcke); + write32(®s->tckesr, param->EmcTckesr); + write32(®s->tpd, param->EmcTpd); + write32(®s->tfaw, param->EmcTfaw); + write32(®s->trpab, param->EmcTrpab); + write32(®s->tclkstable, param->EmcTClkStable); + write32(®s->tclkstop, param->EmcTClkStop); + write32(®s->trefbw, param->EmcTRefBw); + write32(®s->odt_write, param->EmcOdtWrite); + write32(®s->odt_read, param->EmcOdtRead); + write32(®s->fbio_cfg6, param->EmcFbioCfg6); + write32(®s->cfg_dig_dll, param->EmcCfgDigDll); + write32(®s->cfg_dig_dll_period, param->EmcCfgDigDllPeriod); /* Don't write bit 1: addr swizzle lock bit. Written at end of sequence. */ - writel(param->EmcFbioSpare & 0xfffffffd, ®s->fbio_spare); - - writel(param->EmcCfgRsv, ®s->cfg_rsv); - writel(param->EmcDllXformDqs0, ®s->dll_xform_dqs0); - writel(param->EmcDllXformDqs1, ®s->dll_xform_dqs1); - writel(param->EmcDllXformDqs2, ®s->dll_xform_dqs2); - writel(param->EmcDllXformDqs3, ®s->dll_xform_dqs3); - writel(param->EmcDllXformDqs4, ®s->dll_xform_dqs4); - writel(param->EmcDllXformDqs5, ®s->dll_xform_dqs5); - writel(param->EmcDllXformDqs6, ®s->dll_xform_dqs6); - writel(param->EmcDllXformDqs7, ®s->dll_xform_dqs7); - writel(param->EmcDllXformDqs8, ®s->dll_xform_dqs8); - writel(param->EmcDllXformDqs9, ®s->dll_xform_dqs9); - writel(param->EmcDllXformDqs10, ®s->dll_xform_dqs10); - writel(param->EmcDllXformDqs11, ®s->dll_xform_dqs11); - writel(param->EmcDllXformDqs12, ®s->dll_xform_dqs12); - writel(param->EmcDllXformDqs13, ®s->dll_xform_dqs13); - writel(param->EmcDllXformDqs14, ®s->dll_xform_dqs14); - writel(param->EmcDllXformDqs15, ®s->dll_xform_dqs15); - writel(param->EmcDllXformQUse0, ®s->dll_xform_quse0); - writel(param->EmcDllXformQUse1, ®s->dll_xform_quse1); - writel(param->EmcDllXformQUse2, ®s->dll_xform_quse2); - writel(param->EmcDllXformQUse3, ®s->dll_xform_quse3); - writel(param->EmcDllXformQUse4, ®s->dll_xform_quse4); - writel(param->EmcDllXformQUse5, ®s->dll_xform_quse5); - writel(param->EmcDllXformQUse6, ®s->dll_xform_quse6); - writel(param->EmcDllXformQUse7, ®s->dll_xform_quse7); - writel(param->EmcDllXformQUse8, ®s->dll_xform_quse8); - writel(param->EmcDllXformQUse9, ®s->dll_xform_quse9); - writel(param->EmcDllXformQUse10, ®s->dll_xform_quse10); - writel(param->EmcDllXformQUse11, ®s->dll_xform_quse11); - writel(param->EmcDllXformQUse12, ®s->dll_xform_quse12); - writel(param->EmcDllXformQUse13, ®s->dll_xform_quse13); - writel(param->EmcDllXformQUse14, ®s->dll_xform_quse14); - writel(param->EmcDllXformQUse15, ®s->dll_xform_quse15); - writel(param->EmcDllXformDq0, ®s->dll_xform_dq0); - writel(param->EmcDllXformDq1, ®s->dll_xform_dq1); - writel(param->EmcDllXformDq2, ®s->dll_xform_dq2); - writel(param->EmcDllXformDq3, ®s->dll_xform_dq3); - writel(param->EmcDllXformDq4, ®s->dll_xform_dq4); - writel(param->EmcDllXformDq5, ®s->dll_xform_dq5); - writel(param->EmcDllXformDq6, ®s->dll_xform_dq6); - writel(param->EmcDllXformDq7, ®s->dll_xform_dq7); - writel(param->EmcDllXformAddr0, ®s->dll_xform_addr0); - writel(param->EmcDllXformAddr1, ®s->dll_xform_addr1); - writel(param->EmcDllXformAddr2, ®s->dll_xform_addr2); - writel(param->EmcDllXformAddr3, ®s->dll_xform_addr3); - writel(param->EmcDllXformAddr4, ®s->dll_xform_addr4); - writel(param->EmcDllXformAddr5, ®s->dll_xform_addr5); - writel(param->EmcAcpdControl, ®s->acpd_control); - writel(param->EmcDsrVttgenDrv, ®s->dsr_vttgen_drv); - writel(param->EmcTxdsrvttgen, ®s->txdsrvttgen); - writel(param->EmcBgbiasCtl0, ®s->bgbias_ctl0); + write32(®s->fbio_spare, param->EmcFbioSpare & 0xfffffffd); + + write32(®s->cfg_rsv, param->EmcCfgRsv); + write32(®s->dll_xform_dqs0, param->EmcDllXformDqs0); + write32(®s->dll_xform_dqs1, param->EmcDllXformDqs1); + write32(®s->dll_xform_dqs2, param->EmcDllXformDqs2); + write32(®s->dll_xform_dqs3, param->EmcDllXformDqs3); + write32(®s->dll_xform_dqs4, param->EmcDllXformDqs4); + write32(®s->dll_xform_dqs5, param->EmcDllXformDqs5); + write32(®s->dll_xform_dqs6, param->EmcDllXformDqs6); + write32(®s->dll_xform_dqs7, param->EmcDllXformDqs7); + write32(®s->dll_xform_dqs8, param->EmcDllXformDqs8); + write32(®s->dll_xform_dqs9, param->EmcDllXformDqs9); + write32(®s->dll_xform_dqs10, param->EmcDllXformDqs10); + write32(®s->dll_xform_dqs11, param->EmcDllXformDqs11); + write32(®s->dll_xform_dqs12, param->EmcDllXformDqs12); + write32(®s->dll_xform_dqs13, param->EmcDllXformDqs13); + write32(®s->dll_xform_dqs14, param->EmcDllXformDqs14); + write32(®s->dll_xform_dqs15, param->EmcDllXformDqs15); + write32(®s->dll_xform_quse0, param->EmcDllXformQUse0); + write32(®s->dll_xform_quse1, param->EmcDllXformQUse1); + write32(®s->dll_xform_quse2, param->EmcDllXformQUse2); + write32(®s->dll_xform_quse3, param->EmcDllXformQUse3); + write32(®s->dll_xform_quse4, param->EmcDllXformQUse4); + write32(®s->dll_xform_quse5, param->EmcDllXformQUse5); + write32(®s->dll_xform_quse6, param->EmcDllXformQUse6); + write32(®s->dll_xform_quse7, param->EmcDllXformQUse7); + write32(®s->dll_xform_quse8, param->EmcDllXformQUse8); + write32(®s->dll_xform_quse9, param->EmcDllXformQUse9); + write32(®s->dll_xform_quse10, param->EmcDllXformQUse10); + write32(®s->dll_xform_quse11, param->EmcDllXformQUse11); + write32(®s->dll_xform_quse12, param->EmcDllXformQUse12); + write32(®s->dll_xform_quse13, param->EmcDllXformQUse13); + write32(®s->dll_xform_quse14, param->EmcDllXformQUse14); + write32(®s->dll_xform_quse15, param->EmcDllXformQUse15); + write32(®s->dll_xform_dq0, param->EmcDllXformDq0); + write32(®s->dll_xform_dq1, param->EmcDllXformDq1); + write32(®s->dll_xform_dq2, param->EmcDllXformDq2); + write32(®s->dll_xform_dq3, param->EmcDllXformDq3); + write32(®s->dll_xform_dq4, param->EmcDllXformDq4); + write32(®s->dll_xform_dq5, param->EmcDllXformDq5); + write32(®s->dll_xform_dq6, param->EmcDllXformDq6); + write32(®s->dll_xform_dq7, param->EmcDllXformDq7); + write32(®s->dll_xform_addr0, param->EmcDllXformAddr0); + write32(®s->dll_xform_addr1, param->EmcDllXformAddr1); + write32(®s->dll_xform_addr2, param->EmcDllXformAddr2); + write32(®s->dll_xform_addr3, param->EmcDllXformAddr3); + write32(®s->dll_xform_addr4, param->EmcDllXformAddr4); + write32(®s->dll_xform_addr5, param->EmcDllXformAddr5); + write32(®s->acpd_control, param->EmcAcpdControl); + write32(®s->dsr_vttgen_drv, param->EmcDsrVttgenDrv); + write32(®s->txdsrvttgen, param->EmcTxdsrvttgen); + write32(®s->bgbias_ctl0, param->EmcBgbiasCtl0); /* * Set pipe bypass enable bits before sending any DRAM commands. @@ -393,8 +396,8 @@ static void sdram_patch_bootrom(const struct sdram_params *param, BOOT_ROM_PATCH_CONTROL_OFFSET_MASK) >> BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT); addr = BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS + (addr << 2); - writel(param->BootRomPatchData, (uint32_t *)addr); - writel(1, ®s->timing_control); + write32((uint32_t *)addr, param->BootRomPatchData); + write32(®s->timing_control, 1); } } @@ -402,7 +405,7 @@ static void sdram_set_dpd3(const struct sdram_params *param, struct tegra_pmc_regs *regs) { /* Program DPD request */ - writel(param->PmcIoDpd3Req, ®s->io_dpd3_req); + write32(®s->io_dpd3_req, param->PmcIoDpd3Req); udelay(param->PmcIoDpd3ReqWait); } @@ -410,27 +413,27 @@ static void sdram_set_dli_trims(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program DLI trims */ - writel(param->EmcDliTrimTxDqs0, ®s->dli_trim_txdqs0); - writel(param->EmcDliTrimTxDqs1, ®s->dli_trim_txdqs1); - writel(param->EmcDliTrimTxDqs2, ®s->dli_trim_txdqs2); - writel(param->EmcDliTrimTxDqs3, ®s->dli_trim_txdqs3); - writel(param->EmcDliTrimTxDqs4, ®s->dli_trim_txdqs4); - writel(param->EmcDliTrimTxDqs5, ®s->dli_trim_txdqs5); - writel(param->EmcDliTrimTxDqs6, ®s->dli_trim_txdqs6); - writel(param->EmcDliTrimTxDqs7, ®s->dli_trim_txdqs7); - writel(param->EmcDliTrimTxDqs8, ®s->dli_trim_txdqs8); - writel(param->EmcDliTrimTxDqs9, ®s->dli_trim_txdqs9); - writel(param->EmcDliTrimTxDqs10, ®s->dli_trim_txdqs10); - writel(param->EmcDliTrimTxDqs11, ®s->dli_trim_txdqs11); - writel(param->EmcDliTrimTxDqs12, ®s->dli_trim_txdqs12); - writel(param->EmcDliTrimTxDqs13, ®s->dli_trim_txdqs13); - writel(param->EmcDliTrimTxDqs14, ®s->dli_trim_txdqs14); - writel(param->EmcDliTrimTxDqs15, ®s->dli_trim_txdqs15); - - writel(param->EmcCaTrainingTimingCntl1, - ®s->ca_training_timing_cntl1); - writel(param->EmcCaTrainingTimingCntl2, - ®s->ca_training_timing_cntl2); + write32(®s->dli_trim_txdqs0, param->EmcDliTrimTxDqs0); + write32(®s->dli_trim_txdqs1, param->EmcDliTrimTxDqs1); + write32(®s->dli_trim_txdqs2, param->EmcDliTrimTxDqs2); + write32(®s->dli_trim_txdqs3, param->EmcDliTrimTxDqs3); + write32(®s->dli_trim_txdqs4, param->EmcDliTrimTxDqs4); + write32(®s->dli_trim_txdqs5, param->EmcDliTrimTxDqs5); + write32(®s->dli_trim_txdqs6, param->EmcDliTrimTxDqs6); + write32(®s->dli_trim_txdqs7, param->EmcDliTrimTxDqs7); + write32(®s->dli_trim_txdqs8, param->EmcDliTrimTxDqs8); + write32(®s->dli_trim_txdqs9, param->EmcDliTrimTxDqs9); + write32(®s->dli_trim_txdqs10, param->EmcDliTrimTxDqs10); + write32(®s->dli_trim_txdqs11, param->EmcDliTrimTxDqs11); + write32(®s->dli_trim_txdqs12, param->EmcDliTrimTxDqs12); + write32(®s->dli_trim_txdqs13, param->EmcDliTrimTxDqs13); + write32(®s->dli_trim_txdqs14, param->EmcDliTrimTxDqs14); + write32(®s->dli_trim_txdqs15, param->EmcDliTrimTxDqs15); + + write32(®s->ca_training_timing_cntl1, + param->EmcCaTrainingTimingCntl1); + write32(®s->ca_training_timing_cntl2, + param->EmcCaTrainingTimingCntl2); sdram_trigger_emc_timing_update(regs); udelay(param->EmcTimingControlWait); @@ -446,7 +449,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. */ - dummy |= readl(®s->pin); + dummy |= read32(®s->pin); udelay(200 + param->EmcPinExtraWait); /* Deassert reset */ @@ -455,7 +458,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. */ - dummy |= readl(®s->pin); + dummy |= read32(®s->pin); udelay(500 + param->EmcPinExtraWait); /* Enable clock enable signal */ @@ -464,7 +467,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. */ - dummy |= readl(®s->pin); + dummy |= read32(®s->pin); udelay(param->EmcPinProgramWait); if (!dummy) { @@ -478,13 +481,13 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, EMC_NOP_NOP_CMD_MASK | EMC_NOP_NOP_DEV_SELECTN_MASK); /* Write mode registers */ - writel(param->EmcEmrs2, ®s->emrs2); - writel(param->EmcEmrs3, ®s->emrs3); - writel(param->EmcEmrs, ®s->emrs); - writel(param->EmcMrs, ®s->mrs); + write32(®s->emrs2, param->EmcEmrs2); + write32(®s->emrs3, param->EmcEmrs3); + write32(®s->emrs, param->EmcEmrs); + write32(®s->mrs, param->EmcMrs); if (param->EmcExtraModeRegWriteEnable) { - writel(param->EmcMrwExtra, ®s->mrs); + write32(®s->mrs, param->EmcMrwExtra); } } @@ -494,11 +497,11 @@ static void sdram_init_zq_calibration(const struct sdram_params *param, if ((param->EmcZcalWarmColdBootEnables & EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK) == 1) { /* Need to initialize ZCAL on coldboot. */ - writel(param->EmcZcalInitDev0, ®s->zq_cal); + write32(®s->zq_cal, param->EmcZcalInitDev0); udelay(param->EmcZcalInitWait); if ((param->EmcDevSelect & 2) == 0) { - writel(param->EmcZcalInitDev1, ®s->zq_cal); + write32(®s->zq_cal, param->EmcZcalInitDev1); udelay(param->EmcZcalInitWait); } } else { @@ -510,9 +513,9 @@ static void sdram_set_zq_calibration(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Start periodic ZQ calibration */ - writel(param->EmcZcalInterval, ®s->zcal_interval); - writel(param->EmcZcalWaitCnt, ®s->zcal_wait_cnt); - writel(param->EmcZcalMrwCmd, ®s->zcal_mrw_cmd); + write32(®s->zcal_interval, param->EmcZcalInterval); + write32(®s->zcal_wait_cnt, param->EmcZcalWaitCnt); + write32(®s->zcal_mrw_cmd, param->EmcZcalMrwCmd); } static void sdram_set_refresh(const struct sdram_params *param, @@ -530,15 +533,15 @@ static void sdram_set_refresh(const struct sdram_params *param, } /* Enable refresh */ - writel((param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED), - ®s->refctrl); + write32(®s->refctrl, + (param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED)); - writel(param->EmcDynSelfRefControl, ®s->dyn_self_ref_control); - writel(param->EmcCfg, ®s->cfg); - writel(param->EmcSelDpdCtrl, ®s->sel_dpd_ctrl); + write32(®s->dyn_self_ref_control, param->EmcDynSelfRefControl); + write32(®s->cfg, param->EmcCfg); + write32(®s->sel_dpd_ctrl, param->EmcSelDpdCtrl); /* Write addr swizzle lock bit */ - writel(param->EmcFbioSpare, ®s->fbio_spare); + write32(®s->fbio_spare, param->EmcFbioSpare); /* Re-trigger timing to latch power saving functions */ sdram_trigger_emc_timing_update(regs); @@ -556,12 +559,13 @@ static void sdram_lock_carveouts(const struct sdram_params *param, struct tegra_mc_regs *regs) { /* Lock carveouts, and emem_cfg registers */ - writel(param->McVideoProtectWriteAccess, ®s->video_protect_reg_ctrl); - writel(MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED, - ®s->emem_cfg_access_ctrl); - writel(param->McSecCarveoutProtectWriteAccess, - ®s->sec_carveout_reg_ctrl); - writel(param->McMtsCarveoutRegCtrl, ®s->mts_carveout_reg_ctrl); + write32(®s->video_protect_reg_ctrl, + param->McVideoProtectWriteAccess); + write32(®s->emem_cfg_access_ctrl, + MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED); + write32(®s->sec_carveout_reg_ctrl, + param->McSecCarveoutProtectWriteAccess); + write32(®s->mts_carveout_reg_ctrl, param->McMtsCarveoutRegCtrl); } void sdram_init(const struct sdram_params *param) @@ -616,7 +620,7 @@ void sdram_init(const struct sdram_params *param) uint32_t sdram_get_ram_code(void) { struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; - return ((readl(&pmc->strapping_opt_a) & + return ((read32(&pmc->strapping_opt_a) & PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT); } diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 0584177d5e..e1d022a420 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -230,7 +230,7 @@ int spi_claim_bus(struct spi_slave *slave) else val |= SPI_CMD1_CS_SW_VAL; - writel(val, ®s->command1); + write32(®s->command1, val); return 0; } @@ -246,7 +246,7 @@ void spi_release_bus(struct spi_slave *slave) else val &= ~SPI_CMD1_CS_SW_VAL; - writel(val, ®s->command1); + write32(®s->command1, val); } static void dump_fifo_status(struct tegra_spi_channel *spi) @@ -383,12 +383,12 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and * PIO transfers */ - writel(todo - 1, &spi->regs->dma_blk); + write32(&spi->regs->dma_blk, todo - 1); if (dir == SPI_SEND) { unsigned int to_fifo = bytes; while (to_fifo) { - writel(*p, &spi->regs->tx_fifo); + write32(&spi->regs->tx_fifo, *p); p++; to_fifo--; } @@ -493,11 +493,12 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, /* ensure bytes to send will be visible to DMA controller */ dcache_clean_by_mva(spi->out_buf, bytes); - writel((u32)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr); - writel((u32)spi->out_buf, &spi->dma_out->regs->ahb_ptr); + write32(&spi->dma_out->regs->apb_ptr, + (u32)&spi->regs->tx_fifo); + write32(&spi->dma_out->regs->ahb_ptr, (u32)spi->out_buf); setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_out); - writel(wcount, &spi->dma_out->regs->wcount); + write32(&spi->dma_out->regs->wcount, wcount); } else { spi->dma_in = dma_claim(); if (!spi->dma_in) @@ -506,15 +507,15 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, /* avoid data collisions */ dcache_clean_invalidate_by_mva(spi->in_buf, bytes); - writel((u32)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr); - writel((u32)spi->in_buf, &spi->dma_in->regs->ahb_ptr); + write32(&spi->dma_in->regs->apb_ptr, (u32)&spi->regs->rx_fifo); + write32(&spi->dma_in->regs->ahb_ptr, (u32)spi->in_buf); clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_in); - writel(wcount, &spi->dma_in->regs->wcount); + write32(&spi->dma_in->regs->wcount, wcount); } /* BLOCK_SIZE starts at n-1 */ - writel(todo - 1, &spi->regs->dma_blk); + write32(&spi->regs->dma_blk, todo - 1); return todo; } diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index 26aec20030..70fafee83e 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -56,19 +56,19 @@ static void tegra124_uart_init(struct tegra124_uart *uart_ptr) tegra124_uart_tx_flush(uart_ptr); // Disable interrupts. - writeb(0, &uart_ptr->ier); + write8(&uart_ptr->ier, 0); // Force DTR and RTS to high. - writeb(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr); + write8(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS); // Set line configuration, access divisor latches. - writeb(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr); + write8(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config); // Set the divisor. - writeb(divisor & 0xff, &uart_ptr->dll); - writeb((divisor >> 8) & 0xff, &uart_ptr->dlm); + write8(&uart_ptr->dll, divisor & 0xff); + write8(&uart_ptr->dlm, (divisor >> 8) & 0xff); // Hide the divisor latches. - writeb(line_config, &uart_ptr->lcr); + write8(&uart_ptr->lcr, line_config); // Enable FIFOs, and clear receive and transmit. - writeb(UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT, - &uart_ptr->fcr); + write8(&uart_ptr->fcr, + UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); } static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr) @@ -81,7 +81,7 @@ static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr) static void tegra124_uart_tx_byte(struct tegra124_uart *uart_ptr, unsigned char data) { while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE)); - writeb(data, &uart_ptr->thr); + write8(&uart_ptr->thr, data); } static void tegra124_uart_tx_flush(struct tegra124_uart *uart_ptr) diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c index 377d083e02..5940db7067 100644 --- a/src/soc/nvidia/tegra132/addressmap.c +++ b/src/soc/nvidia/tegra132/addressmap.c @@ -187,9 +187,9 @@ void trustzone_region_init(void) return; /* Set the carveout region. */ - writel(tz_base_mib << 20, &mc->security_cfg0); - writel(tz_size_mib, &mc->security_cfg1); + write32(&mc->security_cfg0, tz_base_mib << 20); + write32(&mc->security_cfg1, tz_size_mib); /* Enable SMMU translations */ - writel(MC_SMMU_CONFIG_ENABLE, &mc->smmu_config); + write32(&mc->smmu_config, MC_SMMU_CONFIG_ENABLE); } diff --git a/src/soc/nvidia/tegra132/bootblock.c b/src/soc/nvidia/tegra132/bootblock.c index 6fd36eb2bd..317ab4a1f6 100644 --- a/src/soc/nvidia/tegra132/bootblock.c +++ b/src/soc/nvidia/tegra132/bootblock.c @@ -46,7 +46,7 @@ static void save_odmdata(void) bct_offset = read32((void *)(TEGRA_SRAM_BASE + BCT_OFFSET_IN_BIT)); if (bct_offset > TEGRA_SRAM_BASE && bct_offset < TEGRA_SRAM_MAX) { odmdata = read32((void *)(bct_offset + ODMDATA_OFFSET_IN_BCT)); - writel(odmdata, &pmc->odmdata); + write32(&pmc->odmdata, odmdata); } } diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c index 1cc59add84..f9356a91bc 100644 --- a/src/soc/nvidia/tegra132/ccplex.c +++ b/src/soc/nvidia/tegra132/ccplex.c @@ -46,12 +46,12 @@ static int ccplex_start(void) struct tegra_pmc_regs * const pmc = PMC_REGS; /* Set the handshake bit to be knocked down. */ - writel(handshake_mask, &pmc->scratch118); + write32(&pmc->scratch118, handshake_mask); /* Assert nCXRSET[1] */ reg = read32(CLK_RST_REG(rst_cpu_cmplx_set)); reg |= cxreset1_mask; - writel(reg, CLK_RST_REG(rst_cpu_cmplx_set)); + write32(CLK_RST_REG(rst_cpu_cmplx_set), reg); stopwatch_init_msecs_expire(&sw, timeout_ms); while (1) { @@ -140,14 +140,14 @@ static void request_ram_repair(void) /* Perform cluster 0 ram repair */ reg = read32(&flow->ram_repair); reg |= req; - writel(reg, &flow->ram_repair); + write32(&flow->ram_repair, reg); while ((read32(&flow->ram_repair) & sts) != sts) ; /* Perform cluster 1 ram repair */ reg = read32(&flow->ram_repair_cluster1); reg |= req; - writel(reg, &flow->ram_repair_cluster1); + write32(&flow->ram_repair_cluster1, reg); while ((read32(&flow->ram_repair_cluster1) & sts) != sts) ; @@ -169,11 +169,11 @@ void ccplex_cpu_prepare(void) static void start_common_clocks(void) { /* Clear fast CPU partition reset. */ - writel(CRC_RST_CPUG_CLR_NONCPU, CLK_RST_REG(rst_cpug_cmplx_clr)); + write32(CLK_RST_REG(rst_cpug_cmplx_clr), CRC_RST_CPUG_CLR_NONCPU); /* Clear reset of L2 and CoreSight components. */ - writel(CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG, - CLK_RST_REG(rst_cpug_cmplx_clr)); + write32(CLK_RST_REG(rst_cpug_cmplx_clr), + CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG); } void ccplex_cpu_start(void *entry_addr) diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c index 4cd8a5886d..c13a086501 100644 --- a/src/soc/nvidia/tegra132/clock.c +++ b/src/soc/nvidia/tegra132/clock.c @@ -163,7 +163,7 @@ struct { */ static u32 clock_get_osc_bits(void) { - return (readl(CLK_RST_REG(osc_ctrl)) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; + return (read32(CLK_RST_REG(osc_ctrl)) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; } int clock_get_osc_khz(void) @@ -173,7 +173,7 @@ int clock_get_osc_khz(void) int clock_get_pll_input_khz(void) { - u32 osc_ctrl = readl(CLK_RST_REG(osc_ctrl)); + u32 osc_ctrl = read32(CLK_RST_REG(osc_ctrl)); u32 osc_bits = (osc_ctrl & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; u32 pll_ref_div = (osc_ctrl & OSC_PREDIV_MASK) >> OSC_PREDIV_SHIFT; return osc_table[osc_bits].khz >> pll_ref_div; @@ -186,11 +186,11 @@ void clock_init_arm_generic_timer(void) set_cntfrq(freq); /* Record the system timer frequency. */ - writel(freq, &sysctr->cntfid0); + write32(&sysctr->cntfid0, freq); /* Enable the system counter. */ uint32_t cntcr = read32(&sysctr->cntcr); cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG; - writel(cntcr, &sysctr->cntcr); + write32(&sysctr->cntcr, cntcr); } #define SOR0_CLK_SEL0 (1 << 14) @@ -221,18 +221,18 @@ static void init_pll(u32 *base, u32 *misc, const union pll_fields pll, u32 lock) pll.div.lfcon << PLL_MISC_LFCON_SHIFT; /* Write dividers but BYPASS the PLL while we're messing with it. */ - writel(dividers | PLL_BASE_BYPASS, base); + write32(base, dividers | PLL_BASE_BYPASS); /* * Set Lock bit, CPCON and LFCON fields (default to 0 if it doesn't * exist for this PLL) */ - writel(lock | misc_con, misc); + write32(misc, lock | misc_con); /* Enable PLL and take it back out of BYPASS */ - writel(dividers | PLL_BASE_ENABLE, base); + write32(base, dividers | PLL_BASE_ENABLE); /* Wait for lock ready */ - while (!(readl(base) & PLL_BASE_LOCK)); + while (!(read32(base) & PLL_BASE_LOCK)); } static void init_utmip_pll(void) @@ -243,14 +243,14 @@ static void init_utmip_pll(void) clrbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */ udelay(1); - writel(80 << 16 | 1 << 8 | 0, CLK_RST_REG(utmip_pll_cfg0));/* 960MHz * 1 / 80 == 12 MHz */ + write32(CLK_RST_REG(utmip_pll_cfg0), 80 << 16 | 1 << 8 | 0);/* 960MHz * 1 / 80 == 12 MHz */ - writel(div_round_up(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | div_round_up(khz, 102) << 0 | 0, - CLK_RST_REG(utmip_pll_cfg1)); + write32(CLK_RST_REG(utmip_pll_cfg1), + div_round_up(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | div_round_up(khz, 102) << 0 | 0); /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ - writel(0 << 24 | div_round_up(khz, 3200) << 18 | div_round_up(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0, - CLK_RST_REG(utmip_pll_cfg2)); + write32(CLK_RST_REG(utmip_pll_cfg2), + 0 << 24 | div_round_up(khz, 3200) << 18 | div_round_up(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0); setbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */ } @@ -274,12 +274,12 @@ static void graphics_pll(void) * that it is needed. */ u32 scfg = (1 << 28) | (1 << 24) | (1 << 22); - writel(scfg, cfg); + write32(cfg, scfg); init_pll(CLK_RST_REG(plldp_base), CLK_RST_REG(plldp_misc), osc_table[osc].plldp, PLLDPD2_MISC_LOCK_ENABLE); /* leave dither and undoc bits set, release clamp */ scfg = (1<<28) | (1<<24); - writel(scfg, cfg); + write32(cfg, scfg); } /* @@ -387,8 +387,8 @@ u32 clock_configure_plld(u32 frequency) * been determined through trial and error (must lead to div 13 at 24MHz). */ void clock_early_uart(void) { - writel(CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), - CLK_RST_REG(clk_src_uarta)); + write32(CLK_RST_REG(clk_src_uarta), + CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900)); clock_enable_clear_reset_l(CLK_L_UARTA); } @@ -437,22 +437,22 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, * values after coldboot reset). */ - writel(misc1, CLK_RST_REG(pllm_misc1)); - writel(misc2, CLK_RST_REG(pllm_misc2)); + write32(CLK_RST_REG(pllm_misc1), misc1); + write32(CLK_RST_REG(pllm_misc2), misc2); /* PLLM.BASE needs BYPASS=0, different from general init_pll */ - base = readl(CLK_RST_REG(pllm_base)); + base = read32(CLK_RST_REG(pllm_base)); base &= ~(PLLCMX_BASE_DIVN_MASK | PLLCMX_BASE_DIVM_MASK | PLLM_BASE_DIVP_MASK | PLL_BASE_BYPASS); base |= ((m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) | (p << PLL_BASE_DIVP_SHIFT)); - writel(base, CLK_RST_REG(pllm_base)); + write32(CLK_RST_REG(pllm_base), base); setbits_le32(CLK_RST_REG(pllm_base), PLL_BASE_ENABLE); /* stable_time is required, before we can start to check lock. */ udelay(stable_time); - while (!(readl(CLK_RST_REG(pllm_base)) & PLL_BASE_LOCK)) + while (!(read32(CLK_RST_REG(pllm_base)) & PLL_BASE_LOCK)) udelay(1); /* @@ -466,7 +466,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, /* Enable and start MEM(MC) and EMC. */ clock_enable_clear_reset(0, CLK_H_MEM | CLK_H_EMC, 0, 0, 0, 0); - writel(emc_source, CLK_RST_REG(clk_src_emc)); + write32(CLK_RST_REG(clk_src_emc), emc_source); udelay(IO_STABILIZATION_DELAY); } @@ -477,9 +477,9 @@ void clock_cpu0_config(void) u32 timeout = 0; /* disable IDDQ */ - reg = readl(&clst_clk->pllx_misc3); + reg = read32(&clst_clk->pllx_misc3); reg &= ~PLLX_IDDQ; - writel(reg, &clst_clk->pllx_misc3); + write32(&clst_clk->pllx_misc3, reg); /* init pllx */ init_pll(&clst_clk->pllx_base, &clst_clk->pllx_misc, @@ -490,9 +490,9 @@ void clock_cpu0_config(void) * when above pllx programming has taken effect. */ do { - if (readl(&clst_clk->misc_ctrl) & CLK_SWITCH_MATCH) { - writel((CC_CCLK_BRST_POL_PLLX_OUT0_LJ << 28), - &clst_clk->cclk_brst_pol); + if (read32(&clst_clk->misc_ctrl) & CLK_SWITCH_MATCH) { + write32(&clst_clk->cclk_brst_pol, + (CC_CCLK_BRST_POL_PLLX_OUT0_LJ << 28)); break; } @@ -512,8 +512,8 @@ void clock_cpu0_config(void) void clock_halt_avp(void) { for (;;) - writel(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT, - &flow->halt_cop_events); + write32(&flow->halt_cop_events, + FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT); } void clock_init(void) @@ -521,7 +521,7 @@ void clock_init(void) u32 osc = clock_get_osc_bits(); /* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */ - writel(0x2b << 17 | 0xb << 9, CLK_RST_REG(pllc_misc2)); + write32(CLK_RST_REG(pllc_misc2), 0x2b << 17 | 0xb << 9); /* Max out the AVP clock before everything else (need PLLC for that). */ init_pll(CLK_RST_REG(pllc_base), CLK_RST_REG(pllc_misc), @@ -529,12 +529,12 @@ void clock_init(void) /* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA * features section in the TRM). */ - writel(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT, - CLK_RST_REG(clk_sys_rate)); /* pclk = hclk = sclk/2 */ - writel(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN, - CLK_RST_REG(pllc_out)); - writel(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT, - CLK_RST_REG(sclk_brst_pol)); /* sclk = 300 MHz */ + write32(CLK_RST_REG(clk_sys_rate), + 1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT); /* pclk = hclk = sclk/2 */ + write32(CLK_RST_REG(pllc_out), + CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN); + write32(CLK_RST_REG(sclk_brst_pol), + SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* sclk = 300 MHz */ /* Change the oscillator drive strength (from U-Boot -- why?) */ clrsetbits_le32(CLK_RST_REG(osc_ctrl), OSC_XOFS_MASK, @@ -549,10 +549,10 @@ void clock_init(void) OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT); /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ - writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT, - CLK_RST_REG(pllp_outa)); - writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT, - CLK_RST_REG(pllp_outb)); + write32(CLK_RST_REG(pllp_outa), + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT); + write32(CLK_RST_REG(pllp_outb), + (CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT); /* init pllu */ init_pll(CLK_RST_REG(pllu_base), CLK_RST_REG(pllu_misc), @@ -565,9 +565,9 @@ void clock_init(void) void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, u32 *rst_dev_clr_reg) { - writel(val, clk_enb_set_reg); + write32(clk_enb_set_reg, val); udelay(IO_STABILIZATION_DELAY); - writel(val, rst_dev_clr_reg); + write32(rst_dev_clr_reg, val); } static u32 * const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = { @@ -613,7 +613,7 @@ static void clock_write_regs(u32 * const regs[DEV_CONFIG_BLOCKS], for (; i < DEV_CONFIG_BLOCKS; i++) if (bits[i]) - writel(bits[i], regs[i]); + write32(regs[i], bits[i]); } void clock_enable_regs(u32 bits[DEV_CONFIG_BLOCKS]) @@ -648,9 +648,9 @@ void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x) static void clock_reset_dev(u32 *setaddr, u32 *clraddr, u32 bit) { - writel(bit, setaddr); + write32(setaddr, bit); udelay(LOGIC_STABILIZATION_DELAY); - writel(bit, clraddr); + write32(clraddr, bit); } void clock_reset_l(u32 bit) diff --git a/src/soc/nvidia/tegra132/cpu.c b/src/soc/nvidia/tegra132/cpu.c index 8cd2c0faea..b6f0cfec11 100644 --- a/src/soc/nvidia/tegra132/cpu.c +++ b/src/soc/nvidia/tegra132/cpu.c @@ -40,15 +40,15 @@ static void enable_core_clocks(int cpu) /* Clear reset of CPU components. */ if (cpu == 0) - writel(cpu0_clocks, CLK_RST_REG(rst_cpug_cmplx_clr)); + write32(CLK_RST_REG(rst_cpug_cmplx_clr), cpu0_clocks); else - writel(cpu1_clocks, CLK_RST_REG(rst_cpug_cmplx_clr)); + write32(CLK_RST_REG(rst_cpug_cmplx_clr), cpu1_clocks); } static void set_armv8_32bit_reset_vector(uintptr_t entry) { void * const evp_cpu_reset_vector = EVP_CPU_RESET_VECTOR; - writel(entry, evp_cpu_reset_vector); + write32(evp_cpu_reset_vector, entry); } static void set_armv8_64bit_reset_vector(uintptr_t entry) @@ -56,8 +56,8 @@ static void set_armv8_64bit_reset_vector(uintptr_t entry) struct tegra_pmc_regs * const pmc = PMC_REGS; /* Currently assume 32-bit addresses only. */ - writel(entry, &pmc->secure_scratch34); - writel(0, &pmc->secure_scratch35); + write32(&pmc->secure_scratch34, entry); + write32(&pmc->secure_scratch35, 0); } void cpu_prepare_startup(void *entry_64) diff --git a/src/soc/nvidia/tegra132/dc.c b/src/soc/nvidia/tegra132/dc.c index a3ba9e6fe7..07eac2e687 100644 --- a/src/soc/nvidia/tegra132/dc.c +++ b/src/soc/nvidia/tegra132/dc.c @@ -38,7 +38,7 @@ unsigned long READL(void * p) if (dump > 1) printk(BIOS_SPEW, "readl %p\n", p); - value = readl(p); + value = read32(p); if (dump) printk(BIOS_SPEW, "readl %p %08lx\n", p, value); return value; @@ -48,7 +48,7 @@ void WRITEL(unsigned long value, void * p) { if (dump) printk(BIOS_SPEW, "writel %p %08lx\n", p, value); - writel(value, p); + write32(p, value); } /* return in 1000ths of a Hertz */ diff --git a/src/soc/nvidia/tegra132/dsi.c b/src/soc/nvidia/tegra132/dsi.c index 8508b6666d..1af24e140c 100644 --- a/src/soc/nvidia/tegra132/dsi.c +++ b/src/soc/nvidia/tegra132/dsi.c @@ -869,7 +869,7 @@ static int dsi_enable(struct soc_nvidia_tegra132_config *config) tegra_output_dsi_setup_clock(dsi_a, config); /* configure APB_MISC_GP_MIPI_PAD_CTRL_0 */ - writel(DSIB_MODE_DSI, (unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0); + write32((unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0, DSIB_MODE_DSI); /* configure phy interface timing registers */ tegra_dsi_set_phy_timing(dsi_a); diff --git a/src/soc/nvidia/tegra132/flow_ctrl.c b/src/soc/nvidia/tegra132/flow_ctrl.c index 6d7d11590c..213dca2779 100644 --- a/src/soc/nvidia/tegra132/flow_ctrl.c +++ b/src/soc/nvidia/tegra132/flow_ctrl.c @@ -62,14 +62,14 @@ static uint32_t flowctrl_read_cpu_csr(int cpu) static void flowctrl_write_cpu_csr(int cpu, uint32_t val) { - writel(val, tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]); - val = readl(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]); + write32(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu], val); + val = read32(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]); } void flowctrl_write_cpu_halt(int cpu, uint32_t val) { - writel(val, tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu]); - val = readl(tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu]); + write32(tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu], val); + val = read32(tegra_flowctrl_base + flowctrl_offset_halt_cpu[cpu]); } static void flowctrl_prepare_cpu_off(int cpu) diff --git a/src/soc/nvidia/tegra132/i2c6.c b/src/soc/nvidia/tegra132/i2c6.c index ef86126935..1ae8db3075 100644 --- a/src/soc/nvidia/tegra132/i2c6.c +++ b/src/soc/nvidia/tegra132/i2c6.c @@ -43,7 +43,7 @@ static void remove_clamps(int id) return; /* Remove clamp */ - writel((1 << id), &pmc->remove_clamping_cmd); + write32(&pmc->remove_clamping_cmd, (1 << id)); /* Wait for clamp off */ while (partition_clamp_on(id)) @@ -86,7 +86,7 @@ void soc_configure_i2c6pad(void) soc_configure_host1x(); /* Now we can write the I2C6 mux in DPAUX */ - writel(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL); + write32((void *)DPAUX_HYBRID_PADCTL, I2C6_PADCTL); /* * Delay before turning off Host1X/DPAUX clocks. diff --git a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c index 29fb9dedd6..8392a58228 100644 --- a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c @@ -261,17 +261,17 @@ inline static void write32(uint32_t val, void *addr) inline static void setbits32(uint32_t bits, void *addr) { - writel(read32(addr) | bits, addr); + write32(addr, read32(addr) | bits); } inline static void clrbits32(uint32_t bits, void *addr) { - writel(read32(addr) & ~bits, addr); + write32(addr, read32(addr) & ~bits); } static void __attribute__((noreturn)) reset(void) { - writel(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr); + write32(clk_rst_rst_devices_l_ptr, SWR_TRIG_SYS_RST); halt(); } @@ -370,18 +370,18 @@ static void enable_uart(void) clrbits32(uart_mask, uart_rst_reg); /* Program UART clock source: PLLP (408000000) */ - writel(0, uart_clk_source); + write32(uart_clk_source, 0); /* Program 115200n8 to the uart port */ /* baud-rate of 115200 */ - writel(LCR_DLAB, (uart_base + UART_LCR)); - writel((UART_RATE_115200 & 0xff), (uart_base + UART_THR_DLAB)); - writel((UART_RATE_115200 >> 8), (uart_base + UART_IER_DLAB)); + write32((uart_base + UART_LCR), LCR_DLAB); + write32((uart_base + UART_THR_DLAB), (UART_RATE_115200 & 0xff)); + write32((uart_base + UART_IER_DLAB), (UART_RATE_115200 >> 8)); /* 8-bit and no parity */ - writel(LCR_WD_SIZE_8, (uart_base + UART_LCR)); + write32((uart_base + UART_LCR), LCR_WD_SIZE_8); /* enable and clear RX/TX FIFO */ - writel((FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO), - (uart_base + UART_IIR_FCR)); + write32((uart_base + UART_IIR_FCR), + (FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO)); } /* Accessors. */ @@ -401,7 +401,7 @@ static unsigned get_osc_freq(void) static void enable_jtag(void) { - writel(PP_CONFIG_CTL_JTAG, misc_pp_config_ctl_ptr); + write32(misc_pp_config_ctl_ptr, PP_CONFIG_CTL_JTAG); } /* Clock configuration. */ @@ -417,7 +417,7 @@ static void config_oscillator(void) osc_ctrl &= ~OSC_XOFS_MASK; osc_ctrl |= (xofs << OSC_XOFS_SHIFT); osc_ctrl |= OSC_XOE; - writel(osc_ctrl, clk_rst_osc_ctrl_ptr); + write32(clk_rst_osc_ctrl_ptr, osc_ctrl); } static void config_pllu(void) @@ -462,24 +462,24 @@ static void config_pllu(void) // Configure PLLU. uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE | (divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT); - writel(base, clk_rst_pllu_base_ptr); + write32(clk_rst_pllu_base_ptr, base); uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) | (lfcon << PLLU_LFCON_SHIFT); - writel(misc, clk_rst_pllu_misc_ptr); + write32(clk_rst_pllu_misc_ptr, misc); // Enable PLLU. base &= ~PLLU_BYPASS; base |= PLLU_ENABLE; - writel(base, clk_rst_pllu_base_ptr); + write32(clk_rst_pllu_base_ptr, base); misc |= PLLU_LOCK_ENABLE; - writel(misc, clk_rst_pllu_misc_ptr); + write32(clk_rst_pllu_misc_ptr, misc); } static void enable_cpu_clocks(void) { // Enable the CPU complex clock. - writel(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr); - writel(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr); + write32(clk_rst_clk_enb_l_set_ptr, CLK_ENB_CPU); + write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP); } @@ -489,7 +489,7 @@ static void enable_cpu_clocks(void) static void config_core_sight(void) { // Enable the CoreSight clock. - writel(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr); + write32(clk_rst_clk_out_enb_u_set_ptr, CLK_ENB_CSITE); /* * De-assert CoreSight reset. @@ -497,7 +497,7 @@ static void config_core_sight(void) * now. It will be restored to its original clock source * when the CPU-side restoration code runs. */ - writel(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr); + write32(clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST); } @@ -508,11 +508,11 @@ static void clear_cpu_resets(void) /* Hold CPU1 in reset */ setbits32(SET_CXRESET1, clk_rst_rst_cpulp_cmplx_set_ptr); - writel(CLR_NONCPURESET | CLR_L2RESET | CLR_PRESETDBG, - clk_rst_rst_cpug_cmplx_clr_ptr); + write32(clk_rst_rst_cpug_cmplx_clr_ptr, + CLR_NONCPURESET | CLR_L2RESET | CLR_PRESETDBG); - writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0, - clk_rst_rst_cpug_cmplx_clr_ptr); + write32(clk_rst_rst_cpug_cmplx_clr_ptr, + CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0); } @@ -542,7 +542,8 @@ static void power_on_partition(unsigned id) uint32_t bit = 0x1 << id; if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) { // Partition is not on. Turn it on. - writel(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr); + write32(pmc_ctlr_pwrgate_toggle_ptr, + id | PWRGATE_TOGGLE_START); // Wait until the partition is powerd on. while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) @@ -572,15 +573,15 @@ static void power_on_main_cpu(void) */ uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr); - writel(orig_timer * (204000000 / 32768), - pmc_ctlr_cpupwrgood_timer_ptr); + write32(pmc_ctlr_cpupwrgood_timer_ptr, + orig_timer * (204000000 / 32768)); power_on_partition(PARTID_CRAIL); power_on_partition(PARTID_C0NC); power_on_partition(PARTID_CE0); // Restore the original PMC_CPUPWRGOOD_TIMER. - writel(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr); + write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer); } @@ -609,7 +610,7 @@ void lp0_resume(void) config_oscillator(); // Program SUPER_CCLK_DIVIDER. - writel(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr); + write32(clk_rst_super_cclk_div_ptr, SUPER_CDIV_ENB); config_core_sight(); @@ -623,12 +624,12 @@ void lp0_resume(void) * T132 always resets to AARCH32 and SW needs to write RMR_EL3 * to bootstrap into AARCH64. */ - writel(get_wakeup_vector(), pmc_ctlr_secure_scratch34_ptr); - writel(0, pmc_ctlr_secure_scratch35_ptr); - writel((uint32_t)aarch64_trampoline, evp_cpu_reset_ptr); + write32(pmc_ctlr_secure_scratch34_ptr, get_wakeup_vector()); + write32(pmc_ctlr_secure_scratch35_ptr, 0); + write32(evp_cpu_reset_ptr, (uint32_t)aarch64_trampoline); // Select CPU complex clock source. - writel(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr); + write32(clk_rst_cclk_burst_policy_ptr, CCLK_PLLP_BURST_POLICY); // Disable PLLX since it isn't used as CPU clock source. clrbits32(PLLX_ENABLE, clk_rst_pllx_base_ptr); @@ -637,12 +638,12 @@ void lp0_resume(void) uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr); ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK; ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT; - writel(ack_width, clk_rst_cpu_softrst_ctrl2_ptr); + write32(clk_rst_cpu_softrst_ctrl2_ptr, ack_width); // Disable VPR. - writel(0, mc_video_protect_size_mb_ptr); - writel(VIDEO_PROTECT_WRITE_ACCESS_DISABLE, - mc_video_protect_reg_ctrl_ptr); + write32(mc_video_protect_size_mb_ptr, 0); + write32(mc_video_protect_reg_ctrl_ptr, + VIDEO_PROTECT_WRITE_ACCESS_DISABLE); enable_cpu_clocks(); @@ -655,8 +656,8 @@ void lp0_resume(void) // Halt the AVP. while (1) - writel(FLOW_MODE_STOP | EVENT_JTAG, - flow_ctlr_halt_cop_events_ptr); + write32(flow_ctlr_halt_cop_events_ptr, + FLOW_MODE_STOP | EVENT_JTAG); } diff --git a/src/soc/nvidia/tegra132/mipi.c b/src/soc/nvidia/tegra132/mipi.c index abd2230378..1768fa0fd3 100644 --- a/src/soc/nvidia/tegra132/mipi.c +++ b/src/soc/nvidia/tegra132/mipi.c @@ -43,13 +43,13 @@ static struct tegra_mipi mipi_data = { static inline unsigned long tegra_mipi_readl(struct tegra_mipi *mipi, unsigned long reg) { - return readl(mipi->regs + (reg << 2)); + return read32(mipi->regs + (reg << 2)); } static inline void tegra_mipi_writel(struct tegra_mipi *mipi, unsigned long value, unsigned long reg) { - writel(value, mipi->regs + (reg << 2)); + write32(mipi->regs + (reg << 2), value); } static const struct calibration_regs tegra124_mipi_calibration_regs[] = { diff --git a/src/soc/nvidia/tegra132/padconfig.c b/src/soc/nvidia/tegra132/padconfig.c index 790f10f9c0..46cf944441 100644 --- a/src/soc/nvidia/tegra132/padconfig.c +++ b/src/soc/nvidia/tegra132/padconfig.c @@ -36,7 +36,7 @@ static inline uint32_t pad_get_pinmux(int index) static inline void pad_set_pinmux(int index, uint32_t reg) { - return writel(reg, &pinmux_regs[index]); + return write32(&pinmux_regs[index], reg); } static inline void pad_set_gpio_out(int gpio_index, int val) @@ -45,10 +45,10 @@ static inline void pad_set_gpio_out(int gpio_index, int val) int port = gpio_index_to_port(gpio_index); int bit = gpio_to_bit(gpio_index); - writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (val << bit), - ®s->out_value_mask[port]); - writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (1 << bit), - ®s->out_enable_mask[port]); + write32(®s->out_value_mask[port], + (1 << (bit + GPIO_GPIOS_PER_PORT)) | (val << bit)); + write32(®s->out_enable_mask[port], + (1 << (bit + GPIO_GPIOS_PER_PORT)) | (1 << bit)); } static inline void pad_set_mode(int gpio_index, int sfio_or_gpio) @@ -57,8 +57,8 @@ static inline void pad_set_mode(int gpio_index, int sfio_or_gpio) int port = gpio_index_to_port(gpio_index); int bit = gpio_to_bit(gpio_index); - writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (sfio_or_gpio << bit), - ®s->config_mask[port]); + write32(®s->config_mask[port], + (1 << (bit + GPIO_GPIOS_PER_PORT)) | (sfio_or_gpio << bit)); } static inline void pad_set_gpio_mode(int gpio_index) diff --git a/src/soc/nvidia/tegra132/power.c b/src/soc/nvidia/tegra132/power.c index 0ebfd7c53e..b9ac90acf8 100644 --- a/src/soc/nvidia/tegra132/power.c +++ b/src/soc/nvidia/tegra132/power.c @@ -41,7 +41,7 @@ void power_ungate_partition(uint32_t id) pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK); pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT); pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START; - writel(pwrgate_toggle, &pmc->pwrgate_toggle); + write32(&pmc->pwrgate_toggle, pwrgate_toggle); /* Wait for the request to be accepted. */ while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START) diff --git a/src/soc/nvidia/tegra132/sdram.c b/src/soc/nvidia/tegra132/sdram.c index 14d2b50fe1..65dce9b4cd 100644 --- a/src/soc/nvidia/tegra132/sdram.c +++ b/src/soc/nvidia/tegra132/sdram.c @@ -31,7 +31,7 @@ static void sdram_patch(uintptr_t addr, uint32_t value) { if (addr) - writel(value, (uint32_t*)addr); + write32((uint32_t *)addr, value); } static void writebits(uint32_t value, uint32_t *addr, uint32_t mask) @@ -44,7 +44,7 @@ static void sdram_configure_pmc(const struct sdram_params *param, struct tegra_pmc_regs *regs) { /* VDDP Select */ - writel(param->PmcVddpSel, ®s->vddp_sel); + write32(®s->vddp_sel, param->PmcVddpSel); udelay(param->PmcVddpSelWait); /* Set DDR pad voltage */ @@ -60,7 +60,7 @@ static void sdram_configure_pmc(const struct sdram_params *param, writebits(param->PmcNoIoPower, ®s->no_iopower, (PMC_NO_IOPOWER_MEM_MASK | PMC_NO_IOPOWER_MEM_COMP_MASK)); - writel(param->PmcRegShort, ®s->reg_short); + write32(®s->reg_short, param->PmcRegShort); } static void sdram_start_clocks(const struct sdram_params *param) @@ -100,148 +100,151 @@ static void sdram_deassert_sel_dpd(const struct sdram_params *param, static void sdram_set_swizzle(const struct sdram_params *param, struct tegra_emc_regs *regs) { - writel(param->EmcSwizzleRank0ByteCfg, ®s->swizzle_rank0_byte_cfg); - writel(param->EmcSwizzleRank0Byte0, ®s->swizzle_rank0_byte0); - writel(param->EmcSwizzleRank0Byte1, ®s->swizzle_rank0_byte1); - writel(param->EmcSwizzleRank0Byte2, ®s->swizzle_rank0_byte2); - writel(param->EmcSwizzleRank0Byte3, ®s->swizzle_rank0_byte3); - writel(param->EmcSwizzleRank1ByteCfg, ®s->swizzle_rank1_byte_cfg); - writel(param->EmcSwizzleRank1Byte0, ®s->swizzle_rank1_byte0); - writel(param->EmcSwizzleRank1Byte1, ®s->swizzle_rank1_byte1); - writel(param->EmcSwizzleRank1Byte2, ®s->swizzle_rank1_byte2); - writel(param->EmcSwizzleRank1Byte3, ®s->swizzle_rank1_byte3); + write32(®s->swizzle_rank0_byte_cfg, param->EmcSwizzleRank0ByteCfg); + write32(®s->swizzle_rank0_byte0, param->EmcSwizzleRank0Byte0); + write32(®s->swizzle_rank0_byte1, param->EmcSwizzleRank0Byte1); + write32(®s->swizzle_rank0_byte2, param->EmcSwizzleRank0Byte2); + write32(®s->swizzle_rank0_byte3, param->EmcSwizzleRank0Byte3); + write32(®s->swizzle_rank1_byte_cfg, param->EmcSwizzleRank1ByteCfg); + write32(®s->swizzle_rank1_byte0, param->EmcSwizzleRank1Byte0); + write32(®s->swizzle_rank1_byte1, param->EmcSwizzleRank1Byte1); + write32(®s->swizzle_rank1_byte2, param->EmcSwizzleRank1Byte2); + write32(®s->swizzle_rank1_byte3, param->EmcSwizzleRank1Byte3); } static void sdram_set_pad_controls(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program the pad controls */ - writel(param->EmcXm2CmdPadCtrl, ®s->xm2cmdpadctrl); - writel(param->EmcXm2CmdPadCtrl2, ®s->xm2cmdpadctrl2); - writel(param->EmcXm2CmdPadCtrl3, ®s->xm2cmdpadctrl3); - writel(param->EmcXm2CmdPadCtrl4, ®s->xm2cmdpadctrl4); - writel(param->EmcXm2CmdPadCtrl5, ®s->xm2cmdpadctrl5); + write32(®s->xm2cmdpadctrl, param->EmcXm2CmdPadCtrl); + write32(®s->xm2cmdpadctrl2, param->EmcXm2CmdPadCtrl2); + write32(®s->xm2cmdpadctrl3, param->EmcXm2CmdPadCtrl3); + write32(®s->xm2cmdpadctrl4, param->EmcXm2CmdPadCtrl4); + write32(®s->xm2cmdpadctrl5, param->EmcXm2CmdPadCtrl5); - writel(param->EmcXm2DqsPadCtrl, ®s->xm2dqspadctrl); - writel(param->EmcXm2DqsPadCtrl2, ®s->xm2dqspadctrl2); - writel(param->EmcXm2DqsPadCtrl3, ®s->xm2dqspadctrl3); - writel(param->EmcXm2DqsPadCtrl4, ®s->xm2dqspadctrl4); - writel(param->EmcXm2DqsPadCtrl5, ®s->xm2dqspadctrl5); - writel(param->EmcXm2DqsPadCtrl6, ®s->xm2dqspadctrl6); + write32(®s->xm2dqspadctrl, param->EmcXm2DqsPadCtrl); + write32(®s->xm2dqspadctrl2, param->EmcXm2DqsPadCtrl2); + write32(®s->xm2dqspadctrl3, param->EmcXm2DqsPadCtrl3); + write32(®s->xm2dqspadctrl4, param->EmcXm2DqsPadCtrl4); + write32(®s->xm2dqspadctrl5, param->EmcXm2DqsPadCtrl5); + write32(®s->xm2dqspadctrl6, param->EmcXm2DqsPadCtrl6); - writel(param->EmcXm2DqPadCtrl, ®s->xm2dqpadctrl); - writel(param->EmcXm2DqPadCtrl2, ®s->xm2dqpadctrl2); - writel(param->EmcXm2DqPadCtrl3, ®s->xm2dqpadctrl3); + write32(®s->xm2dqpadctrl, param->EmcXm2DqPadCtrl); + write32(®s->xm2dqpadctrl2, param->EmcXm2DqPadCtrl2); + write32(®s->xm2dqpadctrl3, param->EmcXm2DqPadCtrl3); - writel(param->EmcXm2ClkPadCtrl, ®s->xm2clkpadctrl); - writel(param->EmcXm2ClkPadCtrl2, ®s->xm2clkpadctrl2); + write32(®s->xm2clkpadctrl, param->EmcXm2ClkPadCtrl); + write32(®s->xm2clkpadctrl2, param->EmcXm2ClkPadCtrl2); - writel(param->EmcXm2CompPadCtrl, ®s->xm2comppadctrl); + write32(®s->xm2comppadctrl, param->EmcXm2CompPadCtrl); - writel(param->EmcXm2VttGenPadCtrl, ®s->xm2vttgenpadctrl); - writel(param->EmcXm2VttGenPadCtrl2, ®s->xm2vttgenpadctrl2); - writel(param->EmcXm2VttGenPadCtrl3, ®s->xm2vttgenpadctrl3); + write32(®s->xm2vttgenpadctrl, param->EmcXm2VttGenPadCtrl); + write32(®s->xm2vttgenpadctrl2, param->EmcXm2VttGenPadCtrl2); + write32(®s->xm2vttgenpadctrl3, param->EmcXm2VttGenPadCtrl3); - writel(param->EmcCttTermCtrl, ®s->ctt_term_ctrl); + write32(®s->ctt_term_ctrl, param->EmcCttTermCtrl); } static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs) { - writel(EMC_TIMING_CONTROL_TIMING_UPDATE, ®s->timing_control); + write32(®s->timing_control, EMC_TIMING_CONTROL_TIMING_UPDATE); } static void sdram_init_mc(const struct sdram_params *param, struct tegra_mc_regs *regs) { /* Initialize MC VPR settings */ - writel(param->McDisplaySnapRing, ®s->display_snap_ring); - writel(param->McVideoProtectBom, ®s->video_protect_bom); - writel(param->McVideoProtectBomAdrHi, ®s->video_protect_bom_adr_hi); - writel(param->McVideoProtectSizeMb, ®s->video_protect_size_mb); - writel(param->McVideoProtectVprOverride, - ®s->video_protect_vpr_override); - writel(param->McVideoProtectVprOverride1, - ®s->video_protect_vpr_override1); - writel(param->McVideoProtectGpuOverride0, - ®s->video_protect_gpu_override_0); - writel(param->McVideoProtectGpuOverride1, - ®s->video_protect_gpu_override_1); + write32(®s->display_snap_ring, param->McDisplaySnapRing); + write32(®s->video_protect_bom, param->McVideoProtectBom); + write32(®s->video_protect_bom_adr_hi, + param->McVideoProtectBomAdrHi); + write32(®s->video_protect_size_mb, param->McVideoProtectSizeMb); + write32(®s->video_protect_vpr_override, + param->McVideoProtectVprOverride); + write32(®s->video_protect_vpr_override1, + param->McVideoProtectVprOverride1); + write32(®s->video_protect_gpu_override_0, + param->McVideoProtectGpuOverride0); + write32(®s->video_protect_gpu_override_1, + param->McVideoProtectGpuOverride1); /* Program SDRAM geometry paarameters */ - writel(param->McEmemAdrCfg, ®s->emem_adr_cfg); - writel(param->McEmemAdrCfgDev0, ®s->emem_adr_cfg_dev0); - writel(param->McEmemAdrCfgDev1, ®s->emem_adr_cfg_dev1); + write32(®s->emem_adr_cfg, param->McEmemAdrCfg); + write32(®s->emem_adr_cfg_dev0, param->McEmemAdrCfgDev0); + write32(®s->emem_adr_cfg_dev1, param->McEmemAdrCfgDev1); /* Program bank swizzling */ - writel(param->McEmemAdrCfgBankMask0, ®s->emem_bank_swizzle_cfg0); - writel(param->McEmemAdrCfgBankMask1, ®s->emem_bank_swizzle_cfg1); - writel(param->McEmemAdrCfgBankMask2, ®s->emem_bank_swizzle_cfg2); - writel(param->McEmemAdrCfgBankSwizzle3, ®s->emem_bank_swizzle_cfg3); + write32(®s->emem_bank_swizzle_cfg0, param->McEmemAdrCfgBankMask0); + write32(®s->emem_bank_swizzle_cfg1, param->McEmemAdrCfgBankMask1); + write32(®s->emem_bank_swizzle_cfg2, param->McEmemAdrCfgBankMask2); + write32(®s->emem_bank_swizzle_cfg3, + param->McEmemAdrCfgBankSwizzle3); /* Program external memory aperature (base and size) */ - writel(param->McEmemCfg, ®s->emem_cfg); + write32(®s->emem_cfg, param->McEmemCfg); /* Program SEC carveout (base and size) */ - writel(param->McSecCarveoutBom, ®s->sec_carveout_bom); - writel(param->McSecCarveoutAdrHi, ®s->sec_carveout_adr_hi); - writel(param->McSecCarveoutSizeMb, ®s->sec_carveout_size_mb); + write32(®s->sec_carveout_bom, param->McSecCarveoutBom); + write32(®s->sec_carveout_adr_hi, param->McSecCarveoutAdrHi); + write32(®s->sec_carveout_size_mb, param->McSecCarveoutSizeMb); /* Program MTS carveout (base and size) */ - writel(param->McMtsCarveoutBom, ®s->mts_carveout_bom); - writel(param->McMtsCarveoutAdrHi, ®s->mts_carveout_adr_hi); - writel(param->McMtsCarveoutSizeMb, ®s->mts_carveout_size_mb); + write32(®s->mts_carveout_bom, param->McMtsCarveoutBom); + write32(®s->mts_carveout_adr_hi, param->McMtsCarveoutAdrHi); + write32(®s->mts_carveout_size_mb, param->McMtsCarveoutSizeMb); /* Program the memory arbiter */ - writel(param->McEmemArbCfg, ®s->emem_arb_cfg); - writel(param->McEmemArbOutstandingReq, ®s->emem_arb_outstanding_req); - writel(param->McEmemArbTimingRcd, ®s->emem_arb_timing_rcd); - writel(param->McEmemArbTimingRp, ®s->emem_arb_timing_rp); - writel(param->McEmemArbTimingRc, ®s->emem_arb_timing_rc); - writel(param->McEmemArbTimingRas, ®s->emem_arb_timing_ras); - writel(param->McEmemArbTimingFaw, ®s->emem_arb_timing_faw); - writel(param->McEmemArbTimingRrd, ®s->emem_arb_timing_rrd); - writel(param->McEmemArbTimingRap2Pre, ®s->emem_arb_timing_rap2pre); - writel(param->McEmemArbTimingWap2Pre, ®s->emem_arb_timing_wap2pre); - writel(param->McEmemArbTimingR2R, ®s->emem_arb_timing_r2r); - writel(param->McEmemArbTimingW2W, ®s->emem_arb_timing_w2w); - writel(param->McEmemArbTimingR2W, ®s->emem_arb_timing_r2w); - writel(param->McEmemArbTimingW2R, ®s->emem_arb_timing_w2r); - writel(param->McEmemArbDaTurns, ®s->emem_arb_da_turns); - writel(param->McEmemArbDaCovers, ®s->emem_arb_da_covers); - writel(param->McEmemArbMisc0, ®s->emem_arb_misc0); - writel(param->McEmemArbMisc1, ®s->emem_arb_misc1); - writel(param->McEmemArbRing1Throttle, ®s->emem_arb_ring1_throttle); - writel(param->McEmemArbOverride, ®s->emem_arb_override); - writel(param->McEmemArbOverride1, ®s->emem_arb_override_1); - writel(param->McEmemArbRsv, ®s->emem_arb_rsv); + write32(®s->emem_arb_cfg, param->McEmemArbCfg); + write32(®s->emem_arb_outstanding_req, + param->McEmemArbOutstandingReq); + write32(®s->emem_arb_timing_rcd, param->McEmemArbTimingRcd); + write32(®s->emem_arb_timing_rp, param->McEmemArbTimingRp); + write32(®s->emem_arb_timing_rc, param->McEmemArbTimingRc); + write32(®s->emem_arb_timing_ras, param->McEmemArbTimingRas); + write32(®s->emem_arb_timing_faw, param->McEmemArbTimingFaw); + write32(®s->emem_arb_timing_rrd, param->McEmemArbTimingRrd); + write32(®s->emem_arb_timing_rap2pre, param->McEmemArbTimingRap2Pre); + write32(®s->emem_arb_timing_wap2pre, param->McEmemArbTimingWap2Pre); + write32(®s->emem_arb_timing_r2r, param->McEmemArbTimingR2R); + write32(®s->emem_arb_timing_w2w, param->McEmemArbTimingW2W); + write32(®s->emem_arb_timing_r2w, param->McEmemArbTimingR2W); + write32(®s->emem_arb_timing_w2r, param->McEmemArbTimingW2R); + write32(®s->emem_arb_da_turns, param->McEmemArbDaTurns); + write32(®s->emem_arb_da_covers, param->McEmemArbDaCovers); + write32(®s->emem_arb_misc0, param->McEmemArbMisc0); + write32(®s->emem_arb_misc1, param->McEmemArbMisc1); + write32(®s->emem_arb_ring1_throttle, param->McEmemArbRing1Throttle); + write32(®s->emem_arb_override, param->McEmemArbOverride); + write32(®s->emem_arb_override_1, param->McEmemArbOverride1); + write32(®s->emem_arb_rsv, param->McEmemArbRsv); /* Program extra snap levels for display client */ - writel(param->McDisExtraSnapLevels, ®s->dis_extra_snap_levels); + write32(®s->dis_extra_snap_levels, param->McDisExtraSnapLevels); /* Trigger MC timing update */ - writel(MC_TIMING_CONTROL_TIMING_UPDATE, ®s->timing_control); + write32(®s->timing_control, MC_TIMING_CONTROL_TIMING_UPDATE); /* Program second-level clock enable overrides */ - writel(param->McClkenOverride, ®s->clken_override); + write32(®s->clken_override, param->McClkenOverride); /* Program statistics gathering */ - writel(param->McStatControl, ®s->stat_control); + write32(®s->stat_control, param->McStatControl); } static void sdram_init_emc(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program SDRAM geometry parameters */ - writel(param->EmcAdrCfg, ®s->adr_cfg); + write32(®s->adr_cfg, param->EmcAdrCfg); /* Program second-level clock enable overrides */ - writel(param->EmcClkenOverride, ®s->clken_override); + write32(®s->clken_override, param->EmcClkenOverride); /* Program EMC pad auto calibration */ - writel(param->EmcAutoCalInterval, ®s->auto_cal_interval); - writel(param->EmcAutoCalConfig2, ®s->auto_cal_config2); - writel(param->EmcAutoCalConfig3, ®s->auto_cal_config3); - writel(param->EmcAutoCalConfig, ®s->auto_cal_config); + write32(®s->auto_cal_interval, param->EmcAutoCalInterval); + write32(®s->auto_cal_config2, param->EmcAutoCalConfig2); + write32(®s->auto_cal_config3, param->EmcAutoCalConfig3); + write32(®s->auto_cal_config, param->EmcAutoCalConfig); udelay(param->EmcAutoCalWait); } @@ -249,129 +252,129 @@ static void sdram_set_emc_timing(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program EMC timing configuration */ - writel(param->EmcCfg2, ®s->cfg_2); - writel(param->EmcCfgPipe, ®s->cfg_pipe); - writel(param->EmcDbg, ®s->dbg); - writel(param->EmcCmdQ, ®s->cmdq); - writel(param->EmcMc2EmcQ, ®s->mc2emcq); - writel(param->EmcMrsWaitCnt, ®s->mrs_wait_cnt); - writel(param->EmcMrsWaitCnt2, ®s->mrs_wait_cnt2); - writel(param->EmcFbioCfg5, ®s->fbio_cfg5); - writel(param->EmcRc, ®s->rc); - writel(param->EmcRfc, ®s->rfc); - writel(param->EmcRfcSlr, ®s->rfc_slr); - writel(param->EmcRas, ®s->ras); - writel(param->EmcRp, ®s->rp); - writel(param->EmcR2r, ®s->r2r); - writel(param->EmcW2w, ®s->w2w); - writel(param->EmcR2w, ®s->r2w); - writel(param->EmcW2r, ®s->w2r); - writel(param->EmcR2p, ®s->r2p); - writel(param->EmcW2p, ®s->w2p); - writel(param->EmcRdRcd, ®s->rd_rcd); - writel(param->EmcWrRcd, ®s->wr_rcd); - writel(param->EmcRrd, ®s->rrd); - writel(param->EmcRext, ®s->rext); - writel(param->EmcWext, ®s->wext); - writel(param->EmcWdv, ®s->wdv); - writel(param->EmcWdvMask, ®s->wdv_mask); - writel(param->EmcQUse, ®s->quse); - writel(param->EmcQuseWidth, ®s->quse_width); - writel(param->EmcIbdly, ®s->ibdly); - writel(param->EmcEInput, ®s->einput); - writel(param->EmcEInputDuration, ®s->einput_duration); - writel(param->EmcPutermExtra, ®s->puterm_extra); - writel(param->EmcPutermWidth, ®s->puterm_width); - writel(param->EmcPutermAdj, ®s->puterm_adj); - writel(param->EmcCdbCntl1, ®s->cdb_cntl_1); - writel(param->EmcCdbCntl2, ®s->cdb_cntl_2); - writel(param->EmcCdbCntl3, ®s->cdb_cntl_3); - writel(param->EmcQRst, ®s->qrst); - writel(param->EmcQSafe, ®s->qsafe); - writel(param->EmcRdv, ®s->rdv); - writel(param->EmcRdvMask, ®s->rdv_mask); - writel(param->EmcQpop, ®s->qpop); - writel(param->EmcCtt, ®s->ctt); - writel(param->EmcCttDuration, ®s->ctt_duration); - writel(param->EmcRefresh, ®s->refresh); - writel(param->EmcBurstRefreshNum, ®s->burst_refresh_num); - writel(param->EmcPreRefreshReqCnt, ®s->pre_refresh_req_cnt); - writel(param->EmcPdEx2Wr, ®s->pdex2wr); - writel(param->EmcPdEx2Rd, ®s->pdex2rd); - writel(param->EmcPChg2Pden, ®s->pchg2pden); - writel(param->EmcAct2Pden, ®s->act2pden); - writel(param->EmcAr2Pden, ®s->ar2pden); - writel(param->EmcRw2Pden, ®s->rw2pden); - writel(param->EmcTxsr, ®s->txsr); - writel(param->EmcTxsrDll, ®s->txsrdll); - writel(param->EmcTcke, ®s->tcke); - writel(param->EmcTckesr, ®s->tckesr); - writel(param->EmcTpd, ®s->tpd); - writel(param->EmcTfaw, ®s->tfaw); - writel(param->EmcTrpab, ®s->trpab); - writel(param->EmcTClkStable, ®s->tclkstable); - writel(param->EmcTClkStop, ®s->tclkstop); - writel(param->EmcTRefBw, ®s->trefbw); - writel(param->EmcOdtWrite, ®s->odt_write); - writel(param->EmcOdtRead, ®s->odt_read); - writel(param->EmcFbioCfg6, ®s->fbio_cfg6); - writel(param->EmcCfgDigDll, ®s->cfg_dig_dll); - writel(param->EmcCfgDigDllPeriod, ®s->cfg_dig_dll_period); + write32(®s->cfg_2, param->EmcCfg2); + write32(®s->cfg_pipe, param->EmcCfgPipe); + write32(®s->dbg, param->EmcDbg); + write32(®s->cmdq, param->EmcCmdQ); + write32(®s->mc2emcq, param->EmcMc2EmcQ); + write32(®s->mrs_wait_cnt, param->EmcMrsWaitCnt); + write32(®s->mrs_wait_cnt2, param->EmcMrsWaitCnt2); + write32(®s->fbio_cfg5, param->EmcFbioCfg5); + write32(®s->rc, param->EmcRc); + write32(®s->rfc, param->EmcRfc); + write32(®s->rfc_slr, param->EmcRfcSlr); + write32(®s->ras, param->EmcRas); + write32(®s->rp, param->EmcRp); + write32(®s->r2r, param->EmcR2r); + write32(®s->w2w, param->EmcW2w); + write32(®s->r2w, param->EmcR2w); + write32(®s->w2r, param->EmcW2r); + write32(®s->r2p, param->EmcR2p); + write32(®s->w2p, param->EmcW2p); + write32(®s->rd_rcd, param->EmcRdRcd); + write32(®s->wr_rcd, param->EmcWrRcd); + write32(®s->rrd, param->EmcRrd); + write32(®s->rext, param->EmcRext); + write32(®s->wext, param->EmcWext); + write32(®s->wdv, param->EmcWdv); + write32(®s->wdv_mask, param->EmcWdvMask); + write32(®s->quse, param->EmcQUse); + write32(®s->quse_width, param->EmcQuseWidth); + write32(®s->ibdly, param->EmcIbdly); + write32(®s->einput, param->EmcEInput); + write32(®s->einput_duration, param->EmcEInputDuration); + write32(®s->puterm_extra, param->EmcPutermExtra); + write32(®s->puterm_width, param->EmcPutermWidth); + write32(®s->puterm_adj, param->EmcPutermAdj); + write32(®s->cdb_cntl_1, param->EmcCdbCntl1); + write32(®s->cdb_cntl_2, param->EmcCdbCntl2); + write32(®s->cdb_cntl_3, param->EmcCdbCntl3); + write32(®s->qrst, param->EmcQRst); + write32(®s->qsafe, param->EmcQSafe); + write32(®s->rdv, param->EmcRdv); + write32(®s->rdv_mask, param->EmcRdvMask); + write32(®s->qpop, param->EmcQpop); + write32(®s->ctt, param->EmcCtt); + write32(®s->ctt_duration, param->EmcCttDuration); + write32(®s->refresh, param->EmcRefresh); + write32(®s->burst_refresh_num, param->EmcBurstRefreshNum); + write32(®s->pre_refresh_req_cnt, param->EmcPreRefreshReqCnt); + write32(®s->pdex2wr, param->EmcPdEx2Wr); + write32(®s->pdex2rd, param->EmcPdEx2Rd); + write32(®s->pchg2pden, param->EmcPChg2Pden); + write32(®s->act2pden, param->EmcAct2Pden); + write32(®s->ar2pden, param->EmcAr2Pden); + write32(®s->rw2pden, param->EmcRw2Pden); + write32(®s->txsr, param->EmcTxsr); + write32(®s->txsrdll, param->EmcTxsrDll); + write32(®s->tcke, param->EmcTcke); + write32(®s->tckesr, param->EmcTckesr); + write32(®s->tpd, param->EmcTpd); + write32(®s->tfaw, param->EmcTfaw); + write32(®s->trpab, param->EmcTrpab); + write32(®s->tclkstable, param->EmcTClkStable); + write32(®s->tclkstop, param->EmcTClkStop); + write32(®s->trefbw, param->EmcTRefBw); + write32(®s->odt_write, param->EmcOdtWrite); + write32(®s->odt_read, param->EmcOdtRead); + write32(®s->fbio_cfg6, param->EmcFbioCfg6); + write32(®s->cfg_dig_dll, param->EmcCfgDigDll); + write32(®s->cfg_dig_dll_period, param->EmcCfgDigDllPeriod); /* Don't write bit 1: addr swizzle lock bit. Written at end of sequence. */ - writel(param->EmcFbioSpare & 0xfffffffd, ®s->fbio_spare); - - writel(param->EmcCfgRsv, ®s->cfg_rsv); - writel(param->EmcDllXformDqs0, ®s->dll_xform_dqs0); - writel(param->EmcDllXformDqs1, ®s->dll_xform_dqs1); - writel(param->EmcDllXformDqs2, ®s->dll_xform_dqs2); - writel(param->EmcDllXformDqs3, ®s->dll_xform_dqs3); - writel(param->EmcDllXformDqs4, ®s->dll_xform_dqs4); - writel(param->EmcDllXformDqs5, ®s->dll_xform_dqs5); - writel(param->EmcDllXformDqs6, ®s->dll_xform_dqs6); - writel(param->EmcDllXformDqs7, ®s->dll_xform_dqs7); - writel(param->EmcDllXformDqs8, ®s->dll_xform_dqs8); - writel(param->EmcDllXformDqs9, ®s->dll_xform_dqs9); - writel(param->EmcDllXformDqs10, ®s->dll_xform_dqs10); - writel(param->EmcDllXformDqs11, ®s->dll_xform_dqs11); - writel(param->EmcDllXformDqs12, ®s->dll_xform_dqs12); - writel(param->EmcDllXformDqs13, ®s->dll_xform_dqs13); - writel(param->EmcDllXformDqs14, ®s->dll_xform_dqs14); - writel(param->EmcDllXformDqs15, ®s->dll_xform_dqs15); - writel(param->EmcDllXformQUse0, ®s->dll_xform_quse0); - writel(param->EmcDllXformQUse1, ®s->dll_xform_quse1); - writel(param->EmcDllXformQUse2, ®s->dll_xform_quse2); - writel(param->EmcDllXformQUse3, ®s->dll_xform_quse3); - writel(param->EmcDllXformQUse4, ®s->dll_xform_quse4); - writel(param->EmcDllXformQUse5, ®s->dll_xform_quse5); - writel(param->EmcDllXformQUse6, ®s->dll_xform_quse6); - writel(param->EmcDllXformQUse7, ®s->dll_xform_quse7); - writel(param->EmcDllXformQUse8, ®s->dll_xform_quse8); - writel(param->EmcDllXformQUse9, ®s->dll_xform_quse9); - writel(param->EmcDllXformQUse10, ®s->dll_xform_quse10); - writel(param->EmcDllXformQUse11, ®s->dll_xform_quse11); - writel(param->EmcDllXformQUse12, ®s->dll_xform_quse12); - writel(param->EmcDllXformQUse13, ®s->dll_xform_quse13); - writel(param->EmcDllXformQUse14, ®s->dll_xform_quse14); - writel(param->EmcDllXformQUse15, ®s->dll_xform_quse15); - writel(param->EmcDllXformDq0, ®s->dll_xform_dq0); - writel(param->EmcDllXformDq1, ®s->dll_xform_dq1); - writel(param->EmcDllXformDq2, ®s->dll_xform_dq2); - writel(param->EmcDllXformDq3, ®s->dll_xform_dq3); - writel(param->EmcDllXformDq4, ®s->dll_xform_dq4); - writel(param->EmcDllXformDq5, ®s->dll_xform_dq5); - writel(param->EmcDllXformDq6, ®s->dll_xform_dq6); - writel(param->EmcDllXformDq7, ®s->dll_xform_dq7); - writel(param->EmcDllXformAddr0, ®s->dll_xform_addr0); - writel(param->EmcDllXformAddr1, ®s->dll_xform_addr1); - writel(param->EmcDllXformAddr2, ®s->dll_xform_addr2); - writel(param->EmcDllXformAddr3, ®s->dll_xform_addr3); - writel(param->EmcDllXformAddr4, ®s->dll_xform_addr4); - writel(param->EmcDllXformAddr5, ®s->dll_xform_addr5); - writel(param->EmcAcpdControl, ®s->acpd_control); - writel(param->EmcDsrVttgenDrv, ®s->dsr_vttgen_drv); - writel(param->EmcTxdsrvttgen, ®s->txdsrvttgen); - writel(param->EmcBgbiasCtl0, ®s->bgbias_ctl0); + write32(®s->fbio_spare, param->EmcFbioSpare & 0xfffffffd); + + write32(®s->cfg_rsv, param->EmcCfgRsv); + write32(®s->dll_xform_dqs0, param->EmcDllXformDqs0); + write32(®s->dll_xform_dqs1, param->EmcDllXformDqs1); + write32(®s->dll_xform_dqs2, param->EmcDllXformDqs2); + write32(®s->dll_xform_dqs3, param->EmcDllXformDqs3); + write32(®s->dll_xform_dqs4, param->EmcDllXformDqs4); + write32(®s->dll_xform_dqs5, param->EmcDllXformDqs5); + write32(®s->dll_xform_dqs6, param->EmcDllXformDqs6); + write32(®s->dll_xform_dqs7, param->EmcDllXformDqs7); + write32(®s->dll_xform_dqs8, param->EmcDllXformDqs8); + write32(®s->dll_xform_dqs9, param->EmcDllXformDqs9); + write32(®s->dll_xform_dqs10, param->EmcDllXformDqs10); + write32(®s->dll_xform_dqs11, param->EmcDllXformDqs11); + write32(®s->dll_xform_dqs12, param->EmcDllXformDqs12); + write32(®s->dll_xform_dqs13, param->EmcDllXformDqs13); + write32(®s->dll_xform_dqs14, param->EmcDllXformDqs14); + write32(®s->dll_xform_dqs15, param->EmcDllXformDqs15); + write32(®s->dll_xform_quse0, param->EmcDllXformQUse0); + write32(®s->dll_xform_quse1, param->EmcDllXformQUse1); + write32(®s->dll_xform_quse2, param->EmcDllXformQUse2); + write32(®s->dll_xform_quse3, param->EmcDllXformQUse3); + write32(®s->dll_xform_quse4, param->EmcDllXformQUse4); + write32(®s->dll_xform_quse5, param->EmcDllXformQUse5); + write32(®s->dll_xform_quse6, param->EmcDllXformQUse6); + write32(®s->dll_xform_quse7, param->EmcDllXformQUse7); + write32(®s->dll_xform_quse8, param->EmcDllXformQUse8); + write32(®s->dll_xform_quse9, param->EmcDllXformQUse9); + write32(®s->dll_xform_quse10, param->EmcDllXformQUse10); + write32(®s->dll_xform_quse11, param->EmcDllXformQUse11); + write32(®s->dll_xform_quse12, param->EmcDllXformQUse12); + write32(®s->dll_xform_quse13, param->EmcDllXformQUse13); + write32(®s->dll_xform_quse14, param->EmcDllXformQUse14); + write32(®s->dll_xform_quse15, param->EmcDllXformQUse15); + write32(®s->dll_xform_dq0, param->EmcDllXformDq0); + write32(®s->dll_xform_dq1, param->EmcDllXformDq1); + write32(®s->dll_xform_dq2, param->EmcDllXformDq2); + write32(®s->dll_xform_dq3, param->EmcDllXformDq3); + write32(®s->dll_xform_dq4, param->EmcDllXformDq4); + write32(®s->dll_xform_dq5, param->EmcDllXformDq5); + write32(®s->dll_xform_dq6, param->EmcDllXformDq6); + write32(®s->dll_xform_dq7, param->EmcDllXformDq7); + write32(®s->dll_xform_addr0, param->EmcDllXformAddr0); + write32(®s->dll_xform_addr1, param->EmcDllXformAddr1); + write32(®s->dll_xform_addr2, param->EmcDllXformAddr2); + write32(®s->dll_xform_addr3, param->EmcDllXformAddr3); + write32(®s->dll_xform_addr4, param->EmcDllXformAddr4); + write32(®s->dll_xform_addr5, param->EmcDllXformAddr5); + write32(®s->acpd_control, param->EmcAcpdControl); + write32(®s->dsr_vttgen_drv, param->EmcDsrVttgenDrv); + write32(®s->txdsrvttgen, param->EmcTxdsrvttgen); + write32(®s->bgbias_ctl0, param->EmcBgbiasCtl0); /* * Set pipe bypass enable bits before sending any DRAM commands. @@ -391,8 +394,8 @@ static void sdram_patch_bootrom(const struct sdram_params *param, BOOT_ROM_PATCH_CONTROL_OFFSET_MASK) >> BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT); addr = BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS + (addr << 2); - writel(param->BootRomPatchData, (uint32_t *)addr); - writel(1, ®s->timing_control); + write32((uint32_t *)addr, param->BootRomPatchData); + write32(®s->timing_control, 1); } } @@ -400,7 +403,7 @@ static void sdram_set_dpd3(const struct sdram_params *param, struct tegra_pmc_regs *regs) { /* Program DPD request */ - writel(param->PmcIoDpd3Req, ®s->io_dpd3_req); + write32(®s->io_dpd3_req, param->PmcIoDpd3Req); udelay(param->PmcIoDpd3ReqWait); } @@ -408,27 +411,27 @@ static void sdram_set_dli_trims(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Program DLI trims */ - writel(param->EmcDliTrimTxDqs0, ®s->dli_trim_txdqs0); - writel(param->EmcDliTrimTxDqs1, ®s->dli_trim_txdqs1); - writel(param->EmcDliTrimTxDqs2, ®s->dli_trim_txdqs2); - writel(param->EmcDliTrimTxDqs3, ®s->dli_trim_txdqs3); - writel(param->EmcDliTrimTxDqs4, ®s->dli_trim_txdqs4); - writel(param->EmcDliTrimTxDqs5, ®s->dli_trim_txdqs5); - writel(param->EmcDliTrimTxDqs6, ®s->dli_trim_txdqs6); - writel(param->EmcDliTrimTxDqs7, ®s->dli_trim_txdqs7); - writel(param->EmcDliTrimTxDqs8, ®s->dli_trim_txdqs8); - writel(param->EmcDliTrimTxDqs9, ®s->dli_trim_txdqs9); - writel(param->EmcDliTrimTxDqs10, ®s->dli_trim_txdqs10); - writel(param->EmcDliTrimTxDqs11, ®s->dli_trim_txdqs11); - writel(param->EmcDliTrimTxDqs12, ®s->dli_trim_txdqs12); - writel(param->EmcDliTrimTxDqs13, ®s->dli_trim_txdqs13); - writel(param->EmcDliTrimTxDqs14, ®s->dli_trim_txdqs14); - writel(param->EmcDliTrimTxDqs15, ®s->dli_trim_txdqs15); - - writel(param->EmcCaTrainingTimingCntl1, - ®s->ca_training_timing_cntl1); - writel(param->EmcCaTrainingTimingCntl2, - ®s->ca_training_timing_cntl2); + write32(®s->dli_trim_txdqs0, param->EmcDliTrimTxDqs0); + write32(®s->dli_trim_txdqs1, param->EmcDliTrimTxDqs1); + write32(®s->dli_trim_txdqs2, param->EmcDliTrimTxDqs2); + write32(®s->dli_trim_txdqs3, param->EmcDliTrimTxDqs3); + write32(®s->dli_trim_txdqs4, param->EmcDliTrimTxDqs4); + write32(®s->dli_trim_txdqs5, param->EmcDliTrimTxDqs5); + write32(®s->dli_trim_txdqs6, param->EmcDliTrimTxDqs6); + write32(®s->dli_trim_txdqs7, param->EmcDliTrimTxDqs7); + write32(®s->dli_trim_txdqs8, param->EmcDliTrimTxDqs8); + write32(®s->dli_trim_txdqs9, param->EmcDliTrimTxDqs9); + write32(®s->dli_trim_txdqs10, param->EmcDliTrimTxDqs10); + write32(®s->dli_trim_txdqs11, param->EmcDliTrimTxDqs11); + write32(®s->dli_trim_txdqs12, param->EmcDliTrimTxDqs12); + write32(®s->dli_trim_txdqs13, param->EmcDliTrimTxDqs13); + write32(®s->dli_trim_txdqs14, param->EmcDliTrimTxDqs14); + write32(®s->dli_trim_txdqs15, param->EmcDliTrimTxDqs15); + + write32(®s->ca_training_timing_cntl1, + param->EmcCaTrainingTimingCntl1); + write32(®s->ca_training_timing_cntl2, + param->EmcCaTrainingTimingCntl2); sdram_trigger_emc_timing_update(regs); udelay(param->EmcTimingControlWait); @@ -444,7 +447,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. */ - dummy |= readl(®s->pin); + dummy |= read32(®s->pin); udelay(200 + param->EmcPinExtraWait); /* Deassert reset */ @@ -453,7 +456,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. */ - dummy |= readl(®s->pin); + dummy |= read32(®s->pin); udelay(500 + param->EmcPinExtraWait); /* Enable clock enable signal */ @@ -462,7 +465,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. */ - dummy |= readl(®s->pin); + dummy |= read32(®s->pin); udelay(param->EmcPinProgramWait); if (!dummy) { @@ -479,20 +482,20 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, static void sdram_init_ddr3(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Write mode registers */ - writel(param->EmcEmrs2, ®s->emrs2); - writel(param->EmcEmrs3, ®s->emrs3); - writel(param->EmcEmrs, ®s->emrs); - writel(param->EmcMrs, ®s->mrs); + write32(®s->emrs2, param->EmcEmrs2); + write32(®s->emrs3, param->EmcEmrs3); + write32(®s->emrs, param->EmcEmrs); + write32(®s->mrs, param->EmcMrs); if (param->EmcExtraModeRegWriteEnable) { - writel(param->EmcMrsExtra, ®s->mrs); + write32(®s->mrs, param->EmcMrsExtra); } - writel(param->EmcZcalInitDev0, ®s->zq_cal); + write32(®s->zq_cal, param->EmcZcalInitDev0); udelay(param->EmcZcalInitWait); if ((param->EmcDevSelect & 2) == 0) { - writel(param->EmcZcalInitDev1, ®s->zq_cal); + write32(®s->zq_cal, param->EmcZcalInitDev1); udelay(param->EmcZcalInitWait); } } @@ -500,29 +503,30 @@ static void sdram_init_ddr3(const struct sdram_params *param, struct tegra_emc_r static void sdram_init_lpddr3(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Precharge all banks. DEV_SELECTN = 0 => Select all devices */ - writel(((param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT) | 1), ®s->pre); + write32(®s->pre, + ((param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT) | 1)); /* Send Reset MRW command */ - writel(param->EmcMrwResetCommand, ®s->mrw); + write32(®s->mrw, param->EmcMrwResetCommand); udelay(param->EmcMrwResetNInitWait); - writel(param->EmcZcalInitDev0, ®s->mrw); + write32(®s->mrw, param->EmcZcalInitDev0); udelay(param->EmcZcalInitWait); if ((param->EmcDevSelect & 2) == 0) { - writel(param->EmcZcalInitDev1, ®s->mrw); + write32(®s->mrw, param->EmcZcalInitDev1); udelay(param->EmcZcalInitWait); } /* Write mode registers */ - writel(param->EmcMrw2, ®s->mrw2); - writel(param->EmcMrw1, ®s->mrw); - writel(param->EmcMrw3, ®s->mrw3); - writel(param->EmcMrw4, ®s->mrw4); + write32(®s->mrw2, param->EmcMrw2); + write32(®s->mrw, param->EmcMrw1); + write32(®s->mrw3, param->EmcMrw3); + write32(®s->mrw4, param->EmcMrw4); if (param->EmcExtraModeRegWriteEnable) { - writel(param->EmcMrwExtra, ®s->mrw); + write32(®s->mrw, param->EmcMrwExtra); } } @@ -546,9 +550,9 @@ static void sdram_set_zq_calibration(const struct sdram_params *param, struct tegra_emc_regs *regs) { /* Start periodic ZQ calibration */ - writel(param->EmcZcalInterval, ®s->zcal_interval); - writel(param->EmcZcalWaitCnt, ®s->zcal_wait_cnt); - writel(param->EmcZcalMrwCmd, ®s->zcal_mrw_cmd); + write32(®s->zcal_interval, param->EmcZcalInterval); + write32(®s->zcal_wait_cnt, param->EmcZcalWaitCnt); + write32(®s->zcal_mrw_cmd, param->EmcZcalMrwCmd); } static void sdram_set_refresh(const struct sdram_params *param, @@ -566,15 +570,15 @@ static void sdram_set_refresh(const struct sdram_params *param, } /* Enable refresh */ - writel((param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED), - ®s->refctrl); + write32(®s->refctrl, + (param->EmcDevSelect | EMC_REFCTRL_REF_VALID_ENABLED)); - writel(param->EmcDynSelfRefControl, ®s->dyn_self_ref_control); - writel(param->EmcCfg, ®s->cfg); - writel(param->EmcSelDpdCtrl, ®s->sel_dpd_ctrl); + write32(®s->dyn_self_ref_control, param->EmcDynSelfRefControl); + write32(®s->cfg, param->EmcCfg); + write32(®s->sel_dpd_ctrl, param->EmcSelDpdCtrl); /* Write addr swizzle lock bit */ - writel(param->EmcFbioSpare, ®s->fbio_spare); + write32(®s->fbio_spare, param->EmcFbioSpare); /* Re-trigger timing to latch power saving functions */ sdram_trigger_emc_timing_update(regs); @@ -592,12 +596,13 @@ static void sdram_lock_carveouts(const struct sdram_params *param, struct tegra_mc_regs *regs) { /* Lock carveouts, and emem_cfg registers */ - writel(param->McVideoProtectWriteAccess, ®s->video_protect_reg_ctrl); - writel(MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED, - ®s->emem_cfg_access_ctrl); - writel(param->McSecCarveoutProtectWriteAccess, - ®s->sec_carveout_reg_ctrl); - writel(param->McMtsCarveoutRegCtrl, ®s->mts_carveout_reg_ctrl); + write32(®s->video_protect_reg_ctrl, + param->McVideoProtectWriteAccess); + write32(®s->emem_cfg_access_ctrl, + MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED); + write32(®s->sec_carveout_reg_ctrl, + param->McSecCarveoutProtectWriteAccess); + write32(®s->mts_carveout_reg_ctrl, param->McMtsCarveoutRegCtrl); } void sdram_init(const struct sdram_params *param) @@ -653,7 +658,7 @@ void sdram_init(const struct sdram_params *param) uint32_t sdram_get_ram_code(void) { struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; - return ((readl(&pmc->strapping_opt_a) & + return ((read32(&pmc->strapping_opt_a) & PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT); } diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index 7923f7e3cd..1003ca53a8 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -83,9 +83,9 @@ static void lock_down_vpr(void) { struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE; - writel(0, ®s->video_protect_bom); - writel(0, ®s->video_protect_size_mb); - writel(1, ®s->video_protect_reg_ctrl); + write32(®s->video_protect_bom, 0); + write32(®s->video_protect_size_mb, 0); + write32(®s->video_protect_reg_ctrl, 1); } static void soc_init(device_t dev) diff --git a/src/soc/nvidia/tegra132/spi.c b/src/soc/nvidia/tegra132/spi.c index e240700f06..33620fb202 100644 --- a/src/soc/nvidia/tegra132/spi.c +++ b/src/soc/nvidia/tegra132/spi.c @@ -230,7 +230,7 @@ int spi_claim_bus(struct spi_slave *slave) else val |= SPI_CMD1_CS_SW_VAL; - writel(val, ®s->command1); + write32(®s->command1, val); return 0; } @@ -246,7 +246,7 @@ void spi_release_bus(struct spi_slave *slave) else val &= ~SPI_CMD1_CS_SW_VAL; - writel(val, ®s->command1); + write32(®s->command1, val); } static void dump_fifo_status(struct tegra_spi_channel *spi) @@ -383,12 +383,12 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and * PIO transfers */ - writel(todo - 1, &spi->regs->dma_blk); + write32(&spi->regs->dma_blk, todo - 1); if (dir == SPI_SEND) { unsigned int to_fifo = bytes; while (to_fifo) { - writel(*p, &spi->regs->tx_fifo); + write32(&spi->regs->tx_fifo, *p); p++; to_fifo--; } @@ -493,12 +493,12 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, /* ensure bytes to send will be visible to DMA controller */ dcache_clean_by_mva(spi->out_buf, bytes); - writel((uintptr_t) & spi->regs->tx_fifo, - &spi->dma_out->regs->apb_ptr); - writel((uintptr_t)spi->out_buf, &spi->dma_out->regs->ahb_ptr); + write32(&spi->dma_out->regs->apb_ptr, + (uintptr_t) & spi->regs->tx_fifo); + write32(&spi->dma_out->regs->ahb_ptr, (uintptr_t)spi->out_buf); setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_out); - writel(wcount, &spi->dma_out->regs->wcount); + write32(&spi->dma_out->regs->wcount, wcount); } else { spi->dma_in = dma_claim(); if (!spi->dma_in) @@ -507,16 +507,16 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, /* avoid data collisions */ dcache_clean_invalidate_by_mva(spi->in_buf, bytes); - writel((uintptr_t)&spi->regs->rx_fifo, - &spi->dma_in->regs->apb_ptr); - writel((uintptr_t)spi->in_buf, &spi->dma_in->regs->ahb_ptr); + write32(&spi->dma_in->regs->apb_ptr, + (uintptr_t)&spi->regs->rx_fifo); + write32(&spi->dma_in->regs->ahb_ptr, (uintptr_t)spi->in_buf); clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_in); - writel(wcount, &spi->dma_in->regs->wcount); + write32(&spi->dma_in->regs->wcount, wcount); } /* BLOCK_SIZE starts at n-1 */ - writel(todo - 1, &spi->regs->dma_blk); + write32(&spi->regs->dma_blk, todo - 1); return todo; } diff --git a/src/soc/nvidia/tegra132/uart.c b/src/soc/nvidia/tegra132/uart.c index 90765e1496..e7b7ca9f69 100644 --- a/src/soc/nvidia/tegra132/uart.c +++ b/src/soc/nvidia/tegra132/uart.c @@ -63,19 +63,19 @@ static void tegra132_uart_init(struct tegra132_uart *uart_ptr) tegra132_uart_tx_flush(uart_ptr); // Disable interrupts. - writeb(0, &uart_ptr->ier); + write8(&uart_ptr->ier, 0); // Force DTR and RTS to high. - writeb(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr); + write8(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS); // Set line configuration, access divisor latches. - writeb(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr); + write8(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config); // Set the divisor. - writeb(divisor & 0xff, &uart_ptr->dll); - writeb((divisor >> 8) & 0xff, &uart_ptr->dlm); + write8(&uart_ptr->dll, divisor & 0xff); + write8(&uart_ptr->dlm, (divisor >> 8) & 0xff); // Hide the divisor latches. - writeb(line_config, &uart_ptr->lcr); + write8(&uart_ptr->lcr, line_config); // Enable FIFOs, and clear receive and transmit. - writeb(UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT, - &uart_ptr->fcr); + write8(&uart_ptr->fcr, + UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); } static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr) @@ -88,7 +88,7 @@ static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr) static void tegra132_uart_tx_byte(struct tegra132_uart *uart_ptr, unsigned char data) { while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE)); - writeb(data, &uart_ptr->thr); + write8(&uart_ptr->thr, data); } static void tegra132_uart_tx_flush(struct tegra132_uart *uart_ptr) |