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-rw-r--r--src/soc/nvidia/tegra/i2c.c4
-rw-r--r--src/soc/nvidia/tegra/i2c.h4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c
index 542d4f0fab..6f9142ca6d 100644
--- a/src/soc/nvidia/tegra/i2c.c
+++ b/src/soc/nvidia/tegra/i2c.c
@@ -37,9 +37,9 @@ static void do_bus_clear(int bus)
// 1. Reset the I2C controller (already done)
// 2. Set the # of clock pulses required (using default of 9)
// 3. Select STOP condition (using default of 1 = STOP)
- // 4. Set TERMINATE condition (1 = THRESHOLD)
+ // 4. Set TERMINATE condition (1 = IMMEDIATE)
bc = read32(&regs->bus_clear_config);
- bc |= I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_THRESHOLD;
+ bc |= I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE;
write32(bc, &regs->bus_clear_config);
// 4.1 Set MSTR_CONFIG_LOAD and wait for clear
write32(I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE, &regs->config_load);
diff --git a/src/soc/nvidia/tegra/i2c.h b/src/soc/nvidia/tegra/i2c.h
index 4b1bddd2af..9d7de14a1e 100644
--- a/src/soc/nvidia/tegra/i2c.h
+++ b/src/soc/nvidia/tegra/i2c.h
@@ -115,9 +115,9 @@ enum {
enum {
I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT = 16,
I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_MASK =
- 0x7f << I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT,
+ 0xff << I2C_BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD_SHIFT,
I2C_BUS_CLEAR_CONFIG_BC_STOP_COND_STOP = 0x1 << 2,
- I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_THRESHOLD = 0x1 << 1,
+ I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE = 0x1 << 1,
I2C_BUS_CLEAR_CONFIG_BC_ENABLE = 0x1 << 0,
I2C_BUS_CLEAR_STATUS_CLEARED = 0x1 << 0,