8 files changed, 0 insertions, 449 deletions

diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig
index ee3b80ea85..4420e52e7c 100644
--- a/src/soc/nvidia/tegra132/Kconfig
+++ b/src/soc/nvidia/tegra132/Kconfig
@@ -13,7 +13,6 @@ config SOC_NVIDIA_TEGRA132
 	select HAVE_UART_SPECIAL
 	select ARM_BOOTBLOCK_CUSTOM
 	select SMP
-	select ARM64_USE_SECURE_MONITOR
 	select GENERIC_GPIO_LIB
 	select HAS_PRECBMEM_TIMESTAMP_REGION
 
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index 491b18b5e6..592c34f30a 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -91,16 +91,6 @@ ramstage-y += ramstage.c
 ramstage-y += mmu_operations.c
 ramstage-$(CONFIG_DRIVERS_UART) += uart.c
 ramstage-y += ../tegra/usb.c
-ramstage-$(CONFIG_ARM64_USE_SECURE_MONITOR) += secmon.c
-
-secmon-y += 32bit_reset.S
-secmon-y += cpu.c
-secmon-y += cpu_lib.S
-secmon-y += flow_ctrl.c
-secmon-y += power.c
-secmon-y += psci.c
-secmon-y += uart.c
-secmon-y += gic.c
 
 modules_arm-y += monotonic_timer.c
 
diff --git a/src/soc/nvidia/tegra132/psci.c b/src/soc/nvidia/tegra132/psci.c
deleted file mode 100644
index 3d6c2100a9..0000000000
--- a/src/soc/nvidia/tegra132/psci.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cpu.h>
-#include <arch/io.h>
-#include <arch/psci.h>
-#include <soc/addressmap.h>
-#include <soc/clk_rst.h>
-#include <soc/cpu.h>
-#include <soc/flow_ctrl.h>
-#include <soc/power.h>
-
-#include <console/console.h>
-
-static void *cpu_on_entry_point;
-
-void psci_soc_init(uintptr_t cpu_on_entry)
-{
-	/*
-	 * Stash secmon entry point for CPUs starting up. The 32-bit reset
-	 * vector register is accessible in < EL3 so one has to attempt to
-	 * plug the potential race for that register being changed out from
-	 * under us. Therefore, we set the appropriate registers here, but
-	 * it is also done on each CPU_ON request.
-	 */
-	cpu_on_entry_point = (void *)cpu_on_entry;
-	cpu_prepare_startup(cpu_on_entry_point);
-}
-
-static size_t children_at_level(int parent_level, uint64_t mpidr)
-{
-	if (mpidr != 0)
-		return 0;
-
-	/* T132 just has 2 cores. 0. Level 1 has 2 children at level 0. */
-	switch (parent_level) {
-	case PSCI_AFFINITY_ROOT:
-		return 1;
-	case PSCI_AFFINITY_LEVEL_3:
-		return 1;
-	case PSCI_AFFINITY_LEVEL_2:
-		return 1;
-	case PSCI_AFFINITY_LEVEL_1:
-		return 2;
-	case PSCI_AFFINITY_LEVEL_0:
-		return 0;
-	default:
-		return 0;
-	}
-}
-
-#define TEGRA132_PM_CORE_C7	0x3
-
-static inline void tegra132_enter_sleep(unsigned long pmstate)
-{
-	asm volatile(
-	"       isb\n"
-	"       msr actlr_el1, %0\n"
-	"       wfi\n"
-	:
-	: "r" (pmstate));
-}
-
-static void prepare_cpu_on(int cpu)
-{
-	uint32_t partid;
-
-	partid = cpu ? POWER_PARTID_CE1 : POWER_PARTID_CE0;
-
-	power_ungate_partition(partid);
-	flowctrl_write_cpu_halt(cpu, 0);
-}
-
-static int cmd_prepare(struct psci_cmd *cmd)
-{
-	int ret;
-
-	switch (cmd->type) {
-	case PSCI_CMD_ON:
-		prepare_cpu_on(cmd->target->cpu_state.ci->id);
-		ret = PSCI_RET_SUCCESS;
-		break;
-	case PSCI_CMD_OFF:
-		if (cmd->state_id != -1) {
-			ret = PSCI_RET_INVALID_PARAMETERS;
-			break;
-		}
-		cmd->state_id = TEGRA132_PM_CORE_C7;
-		ret = PSCI_RET_SUCCESS;
-		break;
-	default:
-		ret = PSCI_RET_NOT_SUPPORTED;
-		break;
-	}
-	return ret;
-}
-
-static int cmd_commit(struct psci_cmd *cmd)
-{
-	int ret;
-	struct cpu_info *ci;
-
-	ci = cmd->target->cpu_state.ci;
-
-	switch (cmd->type) {
-	case PSCI_CMD_ON:
-		/* Take CPU out of reset */
-		start_cpu_silent(ci->id, cpu_on_entry_point);
-		ret = PSCI_RET_SUCCESS;
-		break;
-	case PSCI_CMD_OFF:
-		flowctrl_cpu_off(ci->id);
-		tegra132_enter_sleep(cmd->state_id);
-		/* Never reach here */
-		ret = PSCI_RET_NOT_SUPPORTED;
-		printk(BIOS_ERR, "t132 CPU%d PSCI_CMD_OFF fail\n", ci->id);
-		break;
-	default:
-		ret = PSCI_RET_NOT_SUPPORTED;
-		break;
-	}
-	return ret;
-}
-
-struct psci_soc_ops soc_psci_ops = {
-	.children_at_level = &children_at_level,
-	.cmd_prepare = &cmd_prepare,
-	.cmd_commit = &cmd_commit,
-};
diff --git a/src/soc/nvidia/tegra132/secmon.c b/src/soc/nvidia/tegra132/secmon.c
deleted file mode 100644
index ea5467d333..0000000000
--- a/src/soc/nvidia/tegra132/secmon.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/secmon.h>
-#include <console/console.h>
-#include <soc/addressmap.h>
-#include <soc/mmu_operations.h>
-
-static void soc_get_secure_mem(uint64_t *base, size_t *size)
-{
-	uintptr_t tz_base_mib;
-	size_t tz_size_mib;
-
-	carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib);
-
-	tz_base_mib *= MiB;
-	tz_size_mib *= MiB;
-
-	*base = tz_base_mib;
-	*size = tz_size_mib;
-}
-
-void soc_get_secmon_base_size(uint64_t *base, size_t *size)
-{
-	uintptr_t tz_base;
-	size_t ttb_size, tz_size;
-
-	soc_get_secure_mem(&tz_base, &tz_size);
-
-	ttb_size = TTB_SIZE * MiB;
-
-	*base = tz_base + ttb_size;
-	*size = tz_size - ttb_size;
-}
diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc
index 66df6b457d..2898cec780 100644
--- a/src/soc/nvidia/tegra210/Makefile.inc
+++ b/src/soc/nvidia/tegra210/Makefile.inc
@@ -98,19 +98,9 @@ ramstage-y += ramstage.c
 ramstage-y += mmu_operations.c
 ramstage-$(CONFIG_DRIVERS_UART) += uart.c
 ramstage-y += ../tegra/usb.c
-ramstage-$(CONFIG_ARM64_USE_SECURE_MONITOR) += secmon.c
 ramstage-$(CONFIG_HAVE_MTC) += mtc.c
 ramstage-y += stage_entry.S
 
-secmon-y += cpu.c
-secmon-y += cpu_lib.S
-secmon-y += flow_ctrl.c
-secmon-y += power.c
-secmon-y += psci.c
-secmon-y += stage_entry.S
-secmon-y += uart.c
-secmon-y += gic.c
-
 rmodules_arm-y += monotonic_timer.c
 
 CPPFLAGS_common += -Isrc/soc/nvidia/tegra210/include/
diff --git a/src/soc/nvidia/tegra210/ccplex.c b/src/soc/nvidia/tegra210/ccplex.c
index 5e0362338f..a652b7624e 100644
--- a/src/soc/nvidia/tegra210/ccplex.c
+++ b/src/soc/nvidia/tegra210/ccplex.c
@@ -43,11 +43,6 @@ static void enable_cpu_power_partitions(void)
 	power_ungate_partition(POWER_PARTID_CRAIL);
 	power_ungate_partition(POWER_PARTID_C0NC);
 	power_ungate_partition(POWER_PARTID_CE0);
-	if (IS_ENABLED(CONFIG_ARM64_USE_SECURE_MONITOR)) {
-		power_ungate_partition(POWER_PARTID_CE1);
-		power_ungate_partition(POWER_PARTID_CE2);
-		power_ungate_partition(POWER_PARTID_CE3);
-	}
 
 	if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) {
 		/*
diff --git a/src/soc/nvidia/tegra210/psci.c b/src/soc/nvidia/tegra210/psci.c
deleted file mode 100644
index c3a1a7d081..0000000000
--- a/src/soc/nvidia/tegra210/psci.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <assert.h>
-#include <arch/cpu.h>
-#include <arch/io.h>
-#include <arch/psci.h>
-#include <soc/addressmap.h>
-#include <soc/clk_rst.h>
-#include <soc/cpu.h>
-#include <soc/flow_ctrl.h>
-#include <soc/power.h>
-#include <stdlib.h>
-
-#include <console/console.h>
-
-extern void tegra210_reset_handler(void);
-
-#define TEGRA210_PM_STATE_C7	7
-
-static void *cpu_on_entry_point;
-
-void psci_soc_init(uintptr_t cpu_on_entry)
-{
-	/*
-	 * Stash secmon entry point for CPUs starting up. The 32-bit reset
-	 * vector register is accessible in < EL3 so one has to attempt to
-	 * plug the potential race for that register being changed out from
-	 * under us. Therefore, we set the appropriate registers here, but
-	 * it is also done on each CPU_ON request.
-	 */
-	cpu_on_entry_point = tegra210_reset_handler;
-	cpu_prepare_startup(cpu_on_entry_point);
-}
-
-static size_t children_at_level(int parent_level, uint64_t mpidr)
-{
-	if (mpidr != 0)
-		return 0;
-
-	/*
-	 * T210 has 2 clusters. Each cluster has 4 cores. Currently we are
-	 * concentrating only on one of the clusters i.e. A57 cluster. For A53
-	 * bringup, correct the cluster details for A53 cluster as well.
-	 * Since, A57 cluster has 4 cores, level 1 has 4 children at level 0.
-	 * TODO(furquan): Update for A53.
-	 */
-	switch (parent_level) {
-	case PSCI_AFFINITY_ROOT:
-		return 1;
-	case PSCI_AFFINITY_LEVEL_3:
-		return 1;
-	case PSCI_AFFINITY_LEVEL_2:
-		return 1;
-	case PSCI_AFFINITY_LEVEL_1:
-		return 4;
-	case PSCI_AFFINITY_LEVEL_0:
-		return 0;
-	default:
-		return 0;
-	}
-}
-
-static void prepare_cpu_on(int cpu)
-{
-	cpu_prepare_startup(cpu_on_entry_point);
-}
-
-static void prepare_cpu_suspend(int cpu, uint32_t state_id)
-{
-	flowctrl_write_cc4_ctrl(cpu, 0xffffffff);
-	switch (state_id) {
-	case TEGRA210_PM_STATE_C7:
-		flowctrl_cpu_suspend(cpu);
-		break;
-	default:
-		return;
-	}
-}
-
-static void prepare_cpu_resume(int cpu)
-{
-	flowctrl_write_cpu_csr(cpu, 0);
-	flowctrl_write_cpu_halt(cpu, 0);
-	flowctrl_write_cc4_ctrl(cpu, 0);
-}
-
-static void cpu_suspend_commit(int cpu, uint32_t state_id)
-{
-	int l2_flush;
-
-	switch (state_id) {
-	case TEGRA210_PM_STATE_C7:
-		l2_flush = NO_L2_FLUSH;
-		break;
-	default:
-		return;
-	}
-
-	cortex_a57_cpu_power_down(l2_flush);
-	/* should never be here */
-}
-
-static int cmd_prepare(struct psci_cmd *cmd)
-{
-	int ret;
-	struct cpu_info *ci;
-
-	ci = cmd->target->cpu_state.ci;
-
-	switch (cmd->type) {
-	case PSCI_CMD_SUSPEND:
-		cmd->state_id = cmd->state->id;
-		prepare_cpu_on(ci->id);
-		prepare_cpu_suspend(ci->id, cmd->state_id);
-		ret = PSCI_RET_SUCCESS;
-		break;
-	case PSCI_CMD_RESUME:
-		prepare_cpu_resume(ci->id);
-		ret = PSCI_RET_SUCCESS;
-		break;
-	case PSCI_CMD_ON:
-		prepare_cpu_on(ci->id);
-		ret = PSCI_RET_SUCCESS;
-		break;
-	case PSCI_CMD_OFF:
-		if (cmd->state_id != -1) {
-			ret = PSCI_RET_INVALID_PARAMETERS;
-			break;
-		}
-		ret = PSCI_RET_SUCCESS;
-		break;
-	default:
-		ret = PSCI_RET_NOT_SUPPORTED;
-		break;
-	}
-	return ret;
-}
-
-static int cmd_commit(struct psci_cmd *cmd)
-{
-	int ret;
-	struct cpu_info *ci;
-
-	ci = cmd->target->cpu_state.ci;
-
-	switch (cmd->type) {
-	case PSCI_CMD_SUSPEND:
-		cpu_suspend_commit(ci->id, cmd->state_id);
-		ret = PSCI_RET_SUCCESS;
-		break;
-	case PSCI_CMD_RESUME:
-		ret = PSCI_RET_SUCCESS;
-		break;
-	case PSCI_CMD_ON:
-		/* Take CPU out of reset */
-		flowctrl_cpu_on(ci->id);
-		ret = PSCI_RET_SUCCESS;
-		break;
-	case PSCI_CMD_OFF:
-		flowctrl_cpu_off(ci->id);
-		cortex_a57_cpu_power_down(NO_L2_FLUSH);
-		/* Never reach here */
-		ret = PSCI_RET_NOT_SUPPORTED;
-		printk(BIOS_ERR, "t210 CPU%d PSCI_CMD_OFF fail\n", ci->id);
-		break;
-	default:
-		ret = PSCI_RET_NOT_SUPPORTED;
-		break;
-	}
-	return ret;
-}
-
-struct psci_soc_ops soc_psci_ops = {
-	.children_at_level = &children_at_level,
-	.cmd_prepare = &cmd_prepare,
-	.cmd_commit = &cmd_commit,
-};
diff --git a/src/soc/nvidia/tegra210/secmon.c b/src/soc/nvidia/tegra210/secmon.c
deleted file mode 100644
index 392e06c71b..0000000000
--- a/src/soc/nvidia/tegra210/secmon.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/secmon.h>
-#include <console/console.h>
-#include <soc/addressmap.h>
-#include <soc/mmu_operations.h>
-
-static void soc_get_secure_mem(uint64_t *base, size_t *size)
-{
-	uintptr_t tz_base_mib;
-	size_t tz_size_mib;
-
-	carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib);
-
-	tz_base_mib *= MiB;
-	tz_size_mib *= MiB;
-
-	*base = tz_base_mib;
-	*size = tz_size_mib;
-}
-
-void soc_get_secmon_base_size(uint64_t *base, size_t *size)
-{
-	uintptr_t tz_base;
-	size_t ttb_size, tz_size;
-
-	soc_get_secure_mem(&tz_base, &tz_size);
-
-	ttb_size = CONFIG_TTB_SIZE_MB * MiB;
-
-	*base = tz_base + ttb_size;
-	*size = tz_size - ttb_size;
-}