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Diffstat (limited to 'src/soc/qualcomm/ipq806x/clock.c')
-rw-r--r--src/soc/qualcomm/ipq806x/clock.c29
1 files changed, 12 insertions, 17 deletions
diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c
index fe7cfb83a8..0b770da94f 100644
--- a/src/soc/qualcomm/ipq806x/clock.c
+++ b/src/soc/qualcomm/ipq806x/clock.c
@@ -126,22 +126,17 @@ void nand_clock_config(void)
void usb_clock_config(void)
{
/* Magic clock initialization numbers, nobody knows how they work... */
- write32(0x10, USB30_MASTER_CLK_CTL_REG);
- write32(0x10, USB30_1_MASTER_CLK_CTL_REG);
- write32(0x500DF, USB30_MASTER_CLK_MD);
- write32(0xE40942, USB30_MASTER_CLK_NS);
- write32(0x100D7, USB30_MOC_UTMI_CLK_MD);
- write32(0xD80942, USB30_MOC_UTMI_CLK_NS);
- write32(0x10, USB30_MOC_UTMI_CLK_CTL);
- write32(0x10, USB30_1_MOC_UTMI_CLK_CTL);
-
- write32(1 << 5 | /* assert port2 HS PHY async reset */
- 1 << 4 | /* assert master async reset */
- 1 << 3 | /* assert sleep async reset */
- 1 << 2 | /* assert MOC UTMI async reset */
- 1 << 1 | /* assert power-on async reset */
- 1 << 0 | /* assert PHY async reset */
- 0, USB30_RESET);
+ writel(0x10, USB30_MASTER_CLK_CTL_REG);
+ writel(0x10, USB30_1_MASTER_CLK_CTL_REG);
+ writel(0x500DF, USB30_MASTER_CLK_MD);
+ writel(0xE40942, USB30_MASTER_CLK_NS);
+ writel(0x100D7, USB30_MOC_UTMI_CLK_MD);
+ writel(0xD80942, USB30_MOC_UTMI_CLK_NS);
+ writel(0x10, USB30_MOC_UTMI_CLK_CTL);
+ writel(0x10, USB30_1_MOC_UTMI_CLK_CTL);
+
+ writel(1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0 | 0,
+ USB30_RESET);
udelay(5);
- write32(0, USB30_RESET); /* deassert all USB resets again */
+ writel(0, USB30_RESET); /* deassert all USB resets again */
}