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-rw-r--r--src/soc/qualcomm/ipq40xx/spi.c2
-rw-r--r--src/soc/qualcomm/ipq806x/gpio.c16
2 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c
index 4498b31183..d47b9c5995 100644
--- a/src/soc/qualcomm/ipq40xx/spi.c
+++ b/src/soc/qualcomm/ipq40xx/spi.c
@@ -657,7 +657,7 @@ static int spi_ctrlr_setup(const struct spi_slave *slave)
|| ((bus == BLSP1_SPI) && (cs > 0))) {
printk(BIOS_ERR,
"SPI error: unsupported bus %d (Supported busses 0, 1 and 2) "
- "or chipselect\n", bus);
+ "or chipselect\n", bus);
return -1;
}
diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c
index 35a3283bce..15e9e6fbc8 100644
--- a/src/soc/qualcomm/ipq806x/gpio.c
+++ b/src/soc/qualcomm/ipq806x/gpio.c
@@ -63,17 +63,17 @@ void gpio_tlmm_config_set(gpio_t gpio, unsigned func,
unsigned pull, unsigned drvstr,
unsigned enable)
{
- unsigned val = 0;
+ unsigned val = 0;
if (gpio_not_valid(gpio))
return;
- val |= (pull & GPIO_CFG_PULL_MASK) << GPIO_CFG_PULL_SHIFT;
- val |= (func & GPIO_CFG_FUNC_MASK) << GPIO_CFG_FUNC_SHIFT;
- val |= (drvstr & GPIO_CFG_DRV_MASK) << GPIO_CFG_DRV_SHIFT;
- val |= (enable & GPIO_CFG_OE_MASK) << GPIO_CFG_OE_SHIFT;
+ val |= (pull & GPIO_CFG_PULL_MASK) << GPIO_CFG_PULL_SHIFT;
+ val |= (func & GPIO_CFG_FUNC_MASK) << GPIO_CFG_FUNC_SHIFT;
+ val |= (drvstr & GPIO_CFG_DRV_MASK) << GPIO_CFG_DRV_SHIFT;
+ val |= (enable & GPIO_CFG_OE_MASK) << GPIO_CFG_OE_SHIFT;
- write32(GPIO_CONFIG_ADDR(gpio), val);
+ write32(GPIO_CONFIG_ADDR(gpio), val);
}
/*******************************************************
@@ -93,8 +93,8 @@ void gpio_tlmm_config_get(gpio_t gpio, unsigned *func,
unsigned *pull, unsigned *drvstr,
unsigned *enable)
{
- unsigned val;
- void *addr = GPIO_CONFIG_ADDR(gpio);
+ unsigned val;
+ void *addr = GPIO_CONFIG_ADDR(gpio);
if (gpio_not_valid(gpio))
return;