diff options
Diffstat (limited to 'src/soc/rockchip/common')
| -rw-r--r-- | src/soc/rockchip/common/cbmem.c | 24 | ||||
| -rw-r--r-- | src/soc/rockchip/common/include/soc/i2c.h | 23 | ||||
| -rw-r--r-- | src/soc/rockchip/common/include/soc/pwm.h | 21 | ||||
| -rw-r--r-- | src/soc/rockchip/common/include/soc/rk808.h | 23 | ||||
| -rw-r--r-- | src/soc/rockchip/common/include/soc/soc.h | 26 | ||||
| -rw-r--r-- | src/soc/rockchip/common/include/soc/spi.h | 195 | ||||
| -rw-r--r-- | src/soc/rockchip/common/include/soc/tsadc.h | 21 | ||||
| -rw-r--r-- | src/soc/rockchip/common/rk808.c | 203 | ||||
| -rw-r--r-- | src/soc/rockchip/common/spi.c | 286 | ||||
| -rw-r--r-- | src/soc/rockchip/common/uart.c | 163 |
10 files changed, 985 insertions, 0 deletions
diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c new file mode 100644 index 0000000000..d06b292424 --- /dev/null +++ b/src/soc/rockchip/common/cbmem.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <stddef.h> +#include <symbols.h> +#include <soc/sdram.h> + +void *cbmem_top(void) +{ + return _dram + sdram_size_mb()*MiB; +} diff --git a/src/soc/rockchip/common/include/soc/i2c.h b/src/soc/rockchip/common/include/soc/i2c.h new file mode 100644 index 0000000000..4cdcbe04d1 --- /dev/null +++ b/src/soc/rockchip/common/include/soc/i2c.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_I2C_H +#define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_I2C_H + +void i2c_init(unsigned int bus, unsigned int hz); +void software_i2c_attach(unsigned bus); +void software_i2c_detach(unsigned bus); + +#endif /* ! __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_I2C_H */ diff --git a/src/soc/rockchip/common/include/soc/pwm.h b/src/soc/rockchip/common/include/soc/pwm.h new file mode 100644 index 0000000000..4b4b2c0914 --- /dev/null +++ b/src/soc/rockchip/common/include/soc/pwm.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_PWM_H +#define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_PWM_H + +void pwm_init(u32 id, u32 period_ns, u32 duty_ns); + +#endif /* ! __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_PWM_H */ diff --git a/src/soc/rockchip/common/include/soc/rk808.h b/src/soc/rockchip/common/include/soc/rk808.h new file mode 100644 index 0000000000..e9b5ceea7d --- /dev/null +++ b/src/soc/rockchip/common/include/soc/rk808.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_RK808_H +#define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_RK808_H + +void rk808_configure_switch(int sw, int enabled); +void rk808_configure_ldo(int ldo, int millivolts); +void rk808_configure_buck(int buck, int millivolts); + +#endif /* ! __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_RK808_H */ diff --git a/src/soc/rockchip/common/include/soc/soc.h b/src/soc/rockchip/common/include/soc/soc.h new file mode 100644 index 0000000000..465066b8aa --- /dev/null +++ b/src/soc/rockchip/common/include/soc/soc.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SOC_H +#define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SOC_H + +#include <arch/io.h> +#include <symbols.h> + +#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | set) +#define RK_SETBITS(set) RK_CLRSETBITS(0, set) +#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) + +#endif /* ! __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SOC_H */ diff --git a/src/soc/rockchip/common/include/soc/spi.h b/src/soc/rockchip/common/include/soc/spi.h new file mode 100644 index 0000000000..7e9e568e6d --- /dev/null +++ b/src/soc/rockchip/common/include/soc/spi.h @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SPI_H +#define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SPI_H + +/* This driver serves as a CBFS media source. */ +#include <spi-generic.h> +#include <stddef.h> + +struct rockchip_spi { + u32 ctrlr0; + u32 ctrlr1; + u32 spienr; + u32 ser; + u32 baudr; + u32 txftlr; + u32 rxftlr; + u32 txflr; + u32 rxflr; + u32 sr; + u32 ipr; + u32 imr; + u32 isr; + u32 risr; + u32 icr; + u32 dmacr; + u32 damtdlr; + u32 damrdlr; + u32 reserved[(0x400-0x48)/4]; + u32 txdr[0x100]; + u32 rxdr[0x100]; +}; +check_member(rockchip_spi, rxdr, 0x800); + + +#define SF_READ_DATA_CMD 0x3 + +/* --------Bit fields in CTRLR0--------begin */ + +#define SPI_DFS_OFFSET 0 /* Data Frame Size */ +#define SPI_DFS_MASK 0x3 +#define SPI_DFS_4BIT 0x00 +#define SPI_DFS_8BIT 0x01 +#define SPI_DFS_16BIT 0x02 +#define SPI_DFS_RESV 0x03 + +/* Control Frame Size */ +#define SPI_CFS_OFFSET 2 +#define SPI_CFS_MASK 0xF + +/* Serial Clock Phase */ +#define SPI_SCPH_OFFSET 6 +#define SPI_SCPH_MASK 0x1 + +/* Serial clock toggles in middle of first data bit */ +#define SPI_SCPH_TOGMID 0 + +/* Serial clock toggles at start of first data bit */ +#define SPI_SCPH_TOGSTA 1 + +/* Serial Clock Polarity */ +#define SPI_SCOL_OFFSET 7 +#define SPI_SCOL_MASK 0x1 + +/* Inactive state of clock serial clock is low */ +#define SPI_SCOL_LOW 0 + +/* Inactive state of clock serial clock is high */ +#define SPI_SCOL_HIGH 1 + +/* Chip Select Mode */ +#define SPI_CSM_OFFSET 8 +#define SPI_CSM_MASK 0x3 + +/* ss_n keep low after every frame data is transferred */ +#define SPI_CSM_KEEP 0x00 + +/* + * ss_n be high for half sclk_out cycles after + * every frame data is transferred + */ +#define SPI_CSM_HALF 0x01 + +/* ss_n be high for one sclk_out cycle after every frame data is transferred */ +#define SPI_CSM_ONE 0x02 +#define SPI_CSM_RESV 0x03 + +/* SSN to Sclk_out delay */ +#define SPI_SSN_DELAY_OFFSET 10 +#define SPI_SSN_DELAY_MASK 0x1 +/* the peroid between ss_n active and sclk_out active is half sclk_out cycles */ +#define SPI_SSN_DELAY_HALF 0x00 +/* the peroid between ss_n active and sclk_out active is one sclk_out cycle */ +#define SPI_SSN_DELAY_ONE 0x01 + +/* Serial Endian Mode */ +#define SPI_SEM_OFFSET 11 +#define SPI_SEM_MASK 0x1 +/* little endian */ +#define SPI_SEM_LITTLE 0x00 +/* big endian */ +#define SPI_SEM_BIG 0x01 + +/* First Bit Mode */ +#define SPI_FBM_OFFSET 12 +#define SPI_FBM_MASK 0x1 +/* first bit in MSB */ +#define SPI_FBM_MSB 0x00 +/* first bit in LSB */ +#define SPI_FBM_LSB 0x01 + +/* Byte and Halfword Transform */ +#define SPI_HALF_WORLD_TX_OFFSET 13 +#define SPI_HALF_WORLD_MASK 0x1 +/* apb 16bit write/read, spi 8bit write/read */ +#define SPI_APB_16BIT 0x00 +/* apb 8bit write/read, spi 8bit write/read */ +#define SPI_APB_8BIT 0x01 + +/* Rxd Sample Delay */ +#define SPI_RXDSD_OFFSET 14 +#define SPI_RXDSD_MASK 0x3 + +/* Frame Format */ +#define SPI_FRF_OFFSET 16 +#define SPI_FRF_MASK 0x3 +/* motorola spi */ +#define SPI_FRF_SPI 0x00 +/* Texas Instruments SSP*/ +#define SPI_FRF_SSP 0x01 +/* National Semiconductors Microwire */ +#define SPI_FRF_MICROWIRE 0x02 +#define SPI_FRF_RESV 0x03 + +/* Transfer Mode */ +#define SPI_TMOD_OFFSET 18 +#define SPI_TMOD_MASK 0x3 +/* xmit & recv */ +#define SPI_TMOD_TR 0x00 +/* xmit only */ +#define SPI_TMOD_TO 0x01 +/* recv only */ +#define SPI_TMOD_RO 0x02 +#define SPI_TMOD_RESV 0x03 + +/* Operation Mode */ +#define SPI_OMOD_OFFSET 20 +#define SPI_OMOD_MASK 0x1 +/* Master Mode */ +#define SPI_OMOD_MASTER 0x00 +/* Slave Mode */ +#define SPI_OMOD_SLAVE 0x01 + +/* --------Bit fields in CTRLR0--------end */ +/* Bit fields in SR, 7 bits */ +#define SR_MASK 0x7f +#define SR_BUSY (1 << 0) +#define SR_TF_FULL (1 << 1) +#define SR_TF_EMPT (1 << 2) +#define SR_RF_EMPT (1 << 3) +#define SR_RF_FULL (1 << 4) + +/* Bit fields in ISR, IMR, RISR, 7 bits */ +#define SPI_INT_TXEI (1 << 0) +#define SPI_INT_TXOI (1 << 1) +#define SPI_INT_RXUI (1 << 2) +#define SPI_INT_RXOI (1 << 3) +#define SPI_INT_RXFI (1 << 4) + +/* Bit fields in DMACR */ +#define SPI_DMACR_TX_ENABLE (1 << 1) +#define SPI_DMACR_RX_ENABLE (1 << 0) + +/* Bit fields in ICR */ +#define SPI_CLEAR_INT_ALL (1 << 0) +#define SPI_CLEAR_INT_RXUI (1 << 1) +#define SPI_CLEAR_INT_RXOI (1 << 2) +#define SPI_CLEAR_INT_TXOI (1 << 3) + +void rockchip_spi_init(unsigned int bus, unsigned int speed_hz); + +#endif /* ! __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SPI_H */ diff --git a/src/soc/rockchip/common/include/soc/tsadc.h b/src/soc/rockchip/common/include/soc/tsadc.h new file mode 100644 index 0000000000..1728b913ed --- /dev/null +++ b/src/soc/rockchip/common/include/soc/tsadc.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_TSADC_H +#define __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_TSADC_H + +void tsadc_init(void); + +#endif /* ! __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_TSADC_H */ diff --git a/src/soc/rockchip/common/rk808.c b/src/soc/rockchip/common/rk808.c new file mode 100644 index 0000000000..562e76b720 --- /dev/null +++ b/src/soc/rockchip/common/rk808.c @@ -0,0 +1,203 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <bcd.h> +#include <console/console.h> +#include <delay.h> +#include <device/i2c.h> +#include <rtc.h> +#include <soc/rk808.h> +#include <stdint.h> +#include <stdlib.h> + +#if CONFIG_PMIC_BUS < 0 +#error "PMIC_BUS must be set in mainboard's Kconfig." +#endif + +#define RK808_ADDR 0x1b + +#define DCDC_EN 0x23 +#define LDO_EN 0x24 +#define BUCK1SEL 0x2f +#define BUCK4SEL 0x38 +#define LDO_ONSEL(i) (0x39 + 2 * i) +#define LDO_SLPSEL(i) (0x3a + 2 * i) + +#define RTC_SECOND 0x00 +#define RTC_MINUTE 0x01 +#define RTC_HOUR 0x02 +#define RTC_DAY 0x03 +#define RTC_MONTH 0x04 +#define RTC_YEAR 0x05 +#define RTC_WEEKS 0x06 +#define RTC_CTRL 0x10 +#define RTC_STATUS 0x11 + +#define RTC_CTRL_STOP_RTC (1 << 0) +#define RTC_CTRL_GET_TIME (1 << 6) +#define RTC_CTRL_RTC_READSEL (1 << 7) + +#define DCDC_UV_ACT 0x28 +#define DCDC_ILMAX 0x90 + +static int rk808_read(uint8_t reg, uint8_t *value) +{ + return i2c_readb(CONFIG_PMIC_BUS, RK808_ADDR, reg, value); +} + +static int rk808_write(uint8_t reg, uint8_t value) +{ + return i2c_writeb(CONFIG_PMIC_BUS, RK808_ADDR, reg, value); +} + +static void rk808_clrsetbits(uint8_t reg, uint8_t clr, uint8_t set) +{ + uint8_t value; + + if (rk808_read(reg, &value) || rk808_write(reg, (value & ~clr) | set)) + printk(BIOS_ERR, "ERROR: Cannot set Rk808[%#x]!\n", reg); +} + +void rk808_configure_switch(int sw, int enabled) +{ + assert(sw == 1 || sw == 2); + rk808_clrsetbits(DCDC_EN, 1 << (sw + 4), !!enabled << (sw + 4)); +} + +void rk808_configure_ldo(int ldo, int millivolts) +{ + uint8_t vsel; + + if (!millivolts) { + rk808_clrsetbits(LDO_EN, 1 << (ldo - 1), 0); + return; + } + + switch (ldo) { + case 1: + case 2: + case 4: + case 5: + case 8: + vsel = div_round_up(millivolts, 100) - 18; + assert(vsel <= 0x10); + break; + case 3: + case 6: + case 7: + vsel = div_round_up(millivolts, 100) - 8; + assert(vsel <= 0x11); + break; + default: + die("Unknown LDO index!"); + } + + rk808_clrsetbits(LDO_ONSEL(ldo), 0x1f, vsel); + rk808_clrsetbits(LDO_EN, 0, 1 << (ldo - 1)); +} + +void rk808_configure_buck(int buck, int millivolts) +{ + uint8_t vsel; + uint8_t buck_reg; + + switch (buck) { + case 1: + case 2: + /* 25mV steps. base = 29 * 25mV = 725 */ + vsel = (div_round_up(millivolts, 25) - 29) * 2 + 1; + assert(vsel <= 0x3f); + buck_reg = BUCK1SEL + 4 * (buck - 1); + break; + case 4: + vsel = div_round_up(millivolts, 100) - 18; + assert(vsel <= 0xf); + buck_reg = BUCK4SEL; + break; + default: + die("Unknown buck index!"); + } + rk808_clrsetbits(DCDC_ILMAX, 0, 3 << ((buck - 1) * 2)); + + /* undervoltage detection may be wrong, disable it */ + rk808_clrsetbits(DCDC_UV_ACT, 1 << (buck - 1), 0); + + rk808_clrsetbits(buck_reg, 0x3f, vsel); + rk808_clrsetbits(DCDC_EN, 0, 1 << (buck - 1)); +} + +static void rk808rtc_stop(void) +{ + rk808_clrsetbits(RTC_CTRL, RTC_CTRL_STOP_RTC, 0); +} + +static void rk808rtc_start(void) +{ + rk808_clrsetbits(RTC_CTRL, 0, RTC_CTRL_STOP_RTC); +} + +int rtc_set(const struct rtc_time *time) +{ + int ret = 0; + + /* RTC time can only be set when RTC is frozen */ + rk808rtc_stop(); + + ret |= rk808_write(RTC_SECOND, bin2bcd(time->sec)); + ret |= rk808_write(RTC_MINUTE, bin2bcd(time->min)); + ret |= rk808_write(RTC_HOUR, bin2bcd(time->hour)); + ret |= rk808_write(RTC_DAY, bin2bcd(time->mday)); + ret |= rk808_write(RTC_MONTH, bin2bcd(time->mon)); + ret |= rk808_write(RTC_YEAR, bin2bcd(time->year)); + + rk808rtc_start(); + return ret; +} + +int rtc_get(struct rtc_time *time) +{ + uint8_t value; + int ret = 0; + + /* + * Set RTC_READSEL to cause reads to access shadow registers and + * transition GET_TIME from 0 to 1 to cause dynamic register content + * to be copied into shadow registers. This ensures a coherent reading + * of time values as we access each register using slow I2C transfers. + */ + rk808_clrsetbits(RTC_CTRL, RTC_CTRL_GET_TIME, 0); + rk808_clrsetbits(RTC_CTRL, 0, RTC_CTRL_GET_TIME | RTC_CTRL_RTC_READSEL); + + ret |= rk808_read(RTC_SECOND, &value); + time->sec = bcd2bin(value & 0x7f); + + ret |= rk808_read(RTC_MINUTE, &value); + time->min = bcd2bin(value & 0x7f); + + ret |= rk808_read(RTC_HOUR, &value); + time->hour = bcd2bin(value & 0x3f); + + ret |= rk808_read(RTC_DAY, &value); + time->mday = bcd2bin(value & 0x3f); + + ret |= rk808_read(RTC_MONTH, &value); + time->mon = bcd2bin(value & 0x1f); + + ret |= rk808_read(RTC_YEAR, &value); + time->year = bcd2bin(value); + + return ret; +} diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c new file mode 100644 index 0000000000..b08509fe07 --- /dev/null +++ b/src/soc/rockchip/common/spi.c @@ -0,0 +1,286 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <endian.h> +#include <soc/addressmap.h> +#include <soc/spi.h> +#include <soc/clock.h> +#include <spi-generic.h> +#include <spi_flash.h> +#include <stdlib.h> +#include <timer.h> + +struct rockchip_spi_slave { + struct spi_slave slave; + struct rockchip_spi *regs; +}; + +#define SPI_TIMEOUT_US 1000 +#define SPI_SRCCLK_HZ (99*MHz) +#define SPI_FIFO_DEPTH 32 + +static struct rockchip_spi_slave rockchip_spi_slaves[3] = { + { + .slave = { + .bus = 0, + .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, + }, + .regs = (void *)SPI0_BASE, + }, + { + .slave = {.bus = 1, .rw = SPI_READ_FLAG,}, + .regs = (void *)SPI1_BASE, + }, + { + .slave = { + .bus = 2, + .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, + }, + .regs = (void *)SPI2_BASE, + }, + +}; + +static struct rockchip_spi_slave *to_rockchip_spi(struct spi_slave *slave) +{ + return container_of(slave, struct rockchip_spi_slave, slave); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +{ + assert(bus >= 0 && bus < 3); + return &(rockchip_spi_slaves[bus].slave); +} + +static void spi_cs_activate(struct spi_slave *slave) +{ + struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; + setbits_le32(®s->ser, 1); +} + +static void spi_cs_deactivate(struct spi_slave *slave) +{ + struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; + clrbits_le32(®s->ser, 1); +} + +static void rockchip_spi_enable_chip(struct rockchip_spi *regs, int enable) +{ + if (enable == 1) + write32(®s->spienr, 1); + else + write32(®s->spienr, 0); +} + +static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz) +{ + unsigned short clk_div = SPI_SRCCLK_HZ / hz; + assert(clk_div * hz == SPI_SRCCLK_HZ && !(clk_div & 1)); + write32(®s->baudr, clk_div); +} + +void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) +{ + struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs; + unsigned int ctrlr0 = 0; + + rkclk_configure_spi(bus, SPI_SRCCLK_HZ); + rockchip_spi_enable_chip(regs, 0); + rockchip_spi_set_clk(regs, speed_hz); + + /* Operation Mode */ + ctrlr0 = (SPI_OMOD_MASTER << SPI_OMOD_OFFSET); + + /* Data Frame Size */ + ctrlr0 |= SPI_DFS_8BIT << SPI_DFS_OFFSET; + + /* Chip Select Mode */ + ctrlr0 |= (SPI_CSM_KEEP << SPI_CSM_OFFSET); + + /* SSN to Sclk_out delay */ + ctrlr0 |= (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET); + + /* Serial Endian Mode */ + ctrlr0 |= (SPI_SEM_LITTLE << SPI_SEM_OFFSET); + + /* First Bit Mode */ + ctrlr0 |= (SPI_FBM_MSB << SPI_FBM_OFFSET); + + /* Byte and Halfword Transform */ + ctrlr0 |= (SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET); + + /* Rxd Sample Delay */ + ctrlr0 |= (0 << SPI_RXDSD_OFFSET); + + /* Frame Format */ + ctrlr0 |= (SPI_FRF_SPI << SPI_FRF_OFFSET); + + write32(®s->ctrlr0, ctrlr0); + + /* fifo depth */ + write32(®s->txftlr, SPI_FIFO_DEPTH / 2 - 1); + write32(®s->rxftlr, SPI_FIFO_DEPTH / 2 - 1); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + spi_cs_activate(slave); + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + spi_cs_deactivate(slave); +} + +static int rockchip_spi_wait_till_not_busy(struct rockchip_spi *regs) +{ + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, SPI_TIMEOUT_US); + do { + if (!(read32(®s->sr) & SR_BUSY)) + return 0; + } while (!stopwatch_expired(&sw)); + printk(BIOS_DEBUG, + "RK SPI: Status keeps busy for 1000us after a read/write!\n"); + return -1; +} + +static void set_tmod(struct rockchip_spi *regs, unsigned int tmod) +{ + clrsetbits_le32(®s->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET, + tmod << SPI_TMOD_OFFSET); +} + +static void set_transfer_mode(struct rockchip_spi *regs, + unsigned int sout, unsigned int sin) +{ + if (!sin && !sout) + return; + else if (sin && sout) + set_tmod(regs, SPI_TMOD_TR); /* tx and rx */ + else if (!sin) + set_tmod(regs, SPI_TMOD_TO); /* tx only */ + else if (!sout) + set_tmod(regs, SPI_TMOD_RO); /* rx only */ +} + +/* returns 0 to indicate success, <0 otherwise */ +static int do_xfer(struct spi_slave *slave, const void *dout, + unsigned int *bytes_out, void *din, unsigned int *bytes_in) +{ + struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; + uint8_t *in_buf = din; + uint8_t *out_buf = (uint8_t *)dout; + unsigned int min_xfer; + + if (*bytes_out == 0) + min_xfer = *bytes_in; + else if (*bytes_in == 0) + min_xfer = *bytes_out; + else + min_xfer = MIN(*bytes_in, *bytes_out); + + while (min_xfer) { + uint32_t sr = read32(®s->sr); + int xferred = 0; /* in either (or both) directions */ + + if (*bytes_out && !(sr & SR_TF_FULL)) { + write32(®s->txdr, *out_buf); + out_buf++; + *bytes_out -= 1; + xferred = 1; + } + + if (*bytes_in && !(sr & SR_RF_EMPT)) { + *in_buf = read32(®s->rxdr) & 0xff; + in_buf++; + *bytes_in -= 1; + xferred = 1; + } + + min_xfer -= xferred; + } + + if (rockchip_spi_wait_till_not_busy(regs)) { + printk(BIOS_ERR, "Timed out waiting on SPI transfer\n"); + return -1; + } + + return 0; +} + +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return min(65535, buf_len); +} + +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bytes_out, void *din, unsigned int bytes_in) +{ + struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; + int ret = 0; + + /* + * RK3288 SPI controller can transfer up to 65536 data frames (bytes + * in our case) continuously. Break apart large requests as necessary. + * + * FIXME: And by 65536, we really mean 65535. If 0xffff is written to + * ctrlr1, all bytes that we see in rxdr end up being 0x00. 0xffff - 1 + * seems to work fine. + */ + while (bytes_out || bytes_in) { + unsigned int in_now = MIN(bytes_in, 0xffff); + unsigned int out_now = MIN(bytes_out, 0xffff); + unsigned int in_rem, out_rem; + + rockchip_spi_enable_chip(regs, 0); + + /* Enable/disable transmitter and receiver as needed to + * avoid sending or reading spurious bits. */ + set_transfer_mode(regs, bytes_out, bytes_in); + + /* MAX() in case either counter is 0 */ + write32(®s->ctrlr1, MAX(in_now, out_now) - 1); + + rockchip_spi_enable_chip(regs, 1); + + in_rem = in_now; + out_rem = out_now; + ret = do_xfer(slave, dout, &out_rem, din, &in_rem); + if (ret < 0) + break; + + if (bytes_out) { + unsigned int sent = out_now - out_rem; + bytes_out -= sent; + dout += sent; + } + + if (bytes_in) { + unsigned int received = in_now - in_rem; + bytes_in -= received; + din += received; + } + } + + rockchip_spi_enable_chip(regs, 0); + return ret < 0 ? ret : 0; +} diff --git a/src/soc/rockchip/common/uart.c b/src/soc/rockchip/common/uart.c new file mode 100644 index 0000000000..5e1f8ef467 --- /dev/null +++ b/src/soc/rockchip/common/uart.c @@ -0,0 +1,163 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> /* for __console definition */ +#include <console/uart.h> +#include <drivers/uart/uart8250reg.h> +#include <stdint.h> + +/* + * TODO: Use DRIVERS_UART_8250MEM driver instead. + * There is an issue in the IO call functions where x86 and ARM + * ordering is reversed. This 8250MEM driver uses the x86 convention. + * This driver can be replaced once the IO calls are sorted. + */ + +struct rk_uart { + union { + uint32_t thr; /* Transmit holding register. */ + uint32_t rbr; /* Receive buffer register. */ + uint32_t dll; /* Divisor latch lsb. */ + }; + union { + uint32_t ier; /* Interrupt enable register. */ + uint32_t dlm; /* Divisor latch msb. */ + }; + union { + uint32_t iir; /* Interrupt identification register. */ + uint32_t fcr; /* FIFO control register. */ + }; + uint32_t lcr; /* Line control register. */ + uint32_t mcr; /* Modem control register. */ + uint32_t lsr; /* Line status register. */ + uint32_t msr; /* Modem status register. */ + uint32_t scr; + uint32_t reserved1[(0x30 - 0x20) / 4]; + uint32_t srbr[(0x70 - 0x30) / 4]; + uint32_t far; + uint32_t tfr; + uint32_t rfw; + uint32_t usr; + uint32_t tfl; + uint32_t rfl; + uint32_t srr; + uint32_t srts; + uint32_t sbcr; + uint32_t sdmam; + uint32_t sfe; + uint32_t srt; + uint32_t stet; + uint32_t htx; + uint32_t dmasa; + uint32_t reserver2[(0xf4 - 0xac) / 4]; + uint32_t cpr; + uint32_t ucv; + uint32_t ctr; +} __attribute__ ((packed)); + + +static struct rk_uart * const uart_ptr = + (void *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + +static void rk_uart_tx_flush(void); +static int rk_uart_tst_byte(void); + +static void rk_uart_init(void) +{ + /* FIXME: Use a hardcoded divisor for now. + * uint16_t divisor = (u16) uart_baudrate_divisor(default_baudrate(), + * uart_platform_refclk(), 16) + */ + const unsigned divisor = 13; + const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1 + + rk_uart_tx_flush(); + + // Disable interrupts. + write32(&uart_ptr->ier, 0); + // Force DTR and RTS to high. + write32(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS); + // Set line configuration, access divisor latches. + write32(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config); + // Set the divisor. + write32(&uart_ptr->dll, divisor & 0xff); + write32(&uart_ptr->dlm, (divisor >> 8) & 0xff); + // Hide the divisor latches. + write32(&uart_ptr->lcr, line_config); + // Enable FIFOs, and clear receive and transmit. + write32(&uart_ptr->fcr, UART8250_FCR_FIFO_EN | + UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT); +} + +static void rk_uart_tx_byte(unsigned char data) +{ + while (!(read32(&uart_ptr->lsr) & UART8250_LSR_THRE)); + write32(&uart_ptr->thr, data); +} + +static void rk_uart_tx_flush(void) +{ + while (!(read32(&uart_ptr->lsr) & UART8250_LSR_TEMT)); +} + +static unsigned char rk_uart_rx_byte(void) +{ + if (!rk_uart_tst_byte()) + return 0; + return read32(&uart_ptr->rbr); +} + +static int rk_uart_tst_byte(void) +{ + return (read32(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; +} + + + +void uart_init(int idx) +{ + rk_uart_init(); +} + +unsigned char uart_rx_byte(int idx) +{ + return rk_uart_rx_byte(); +} + +void uart_tx_byte(int idx, unsigned char data) +{ + rk_uart_tx_byte(data); +} + +void uart_tx_flush(int idx) +{ + rk_uart_tx_flush(); +} + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + serial.baud = default_baudrate(); + serial.regwidth = 4; + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif |