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-rw-r--r--src/soc/rockchip/rk3288/cbmem.c4
-rw-r--r--src/soc/rockchip/rk3288/include/soc/memlayout.ld1
-rw-r--r--src/soc/rockchip/rk3288/include/soc/soc.h8
-rw-r--r--src/soc/rockchip/rk3288/soc.c12
4 files changed, 8 insertions, 17 deletions
diff --git a/src/soc/rockchip/rk3288/cbmem.c b/src/soc/rockchip/rk3288/cbmem.c
index 1c3a902d0e..2eed97281a 100644
--- a/src/soc/rockchip/rk3288/cbmem.c
+++ b/src/soc/rockchip/rk3288/cbmem.c
@@ -18,11 +18,11 @@
*/
#include <cbmem.h>
-#include <soc/soc.h>
#include <stddef.h>
+#include <symbols.h>
void *cbmem_top(void)
{
- return (void *)(get_fb_base_kb()*KiB);
+ return _dram + (size_t)CONFIG_DRAM_SIZE_MB*MiB;
}
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 7a8b77ccaa..f5d3ca84d4 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -31,6 +31,7 @@ SECTIONS
RAMSTAGE(0x00200000, 128K)
POSTRAM_CBFS_CACHE(0x01000000, 1M)
DMA_COHERENT(0x10000000, 2M)
+ FRAMEBUFFER(0x10800000, 8M)
SRAM_START(0xFF700000)
TTB(0xFF700000, 16K)
diff --git a/src/soc/rockchip/rk3288/include/soc/soc.h b/src/soc/rockchip/rk3288/include/soc/soc.h
index c6ab7f46f6..05f54da1c3 100644
--- a/src/soc/rockchip/rk3288/include/soc/soc.h
+++ b/src/soc/rockchip/rk3288/include/soc/soc.h
@@ -27,12 +27,4 @@
#define RK_SETBITS(set) RK_CLRSETBITS(0, set)
#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0)
-#define FB_SIZE_KB 8192
-#define RAM_BASE_KB ((uintptr_t)_dram >> 10)
-#define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL)
-
-static inline u32 get_fb_base_kb(void)
-{
- return RAM_BASE_KB + RAM_SIZE_KB - FB_SIZE_KB;
-}
#endif
diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c
index abd93d70f0..fa26c6db36 100644
--- a/src/soc/rockchip/rk3288/soc.c
+++ b/src/soc/rockchip/rk3288/soc.c
@@ -28,30 +28,28 @@
#include <stddef.h>
#include <stdlib.h>
#include <string.h>
+#include <symbols.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "chip.h"
static void soc_init(device_t dev)
{
- unsigned long fb_size = FB_SIZE_KB * KiB;
- u32 lcdbase = get_fb_base_kb() * KiB;
-
- ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB);
- mmio_resource(dev, 1, lcdbase / KiB, fb_size / KiB);
+ ram_resource(dev, 0, (uintptr_t)_dram/KiB,
+ CONFIG_DRAM_SIZE_MB*(MiB/KiB));
if (vboot_skip_display_init())
printk(BIOS_INFO, "Skipping display init.\n");
#if !IS_ENABLED(CONFIG_SKIP_DISPLAY_INIT_HACK)
else
- rk_display_init(dev, lcdbase, fb_size);
+ rk_display_init(dev, (uintptr_t)_framebuffer,
+ _framebuffer_size);
#endif
}
static struct device_operations soc_ops = {
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
.init = soc_init,
.scan_bus = 0,
};