summaryrefslogtreecommitdiff
path: root/src/soc/rockchip/rk3288
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/rockchip/rk3288')
-rw-r--r--src/soc/rockchip/rk3288/bootblock.c2
-rw-r--r--src/soc/rockchip/rk3288/soc.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c
index 7308241e17..5ccfebd583 100644
--- a/src/soc/rockchip/rk3288/bootblock.c
+++ b/src/soc/rockchip/rk3288/bootblock.c
@@ -33,7 +33,7 @@ void bootblock_soc_init(void)
/* SRAM is tightly wedged between registers, need to use subtables. Map
* write-through as equivalent for non-cacheable without XN on A17. */
mmu_config_range_kb((uintptr_t)_sram/KiB,
- _sram_size/KiB, DCACHE_WRITETHROUGH);
+ REGION_SIZE(sram)/KiB, DCACHE_WRITETHROUGH);
dcache_mmu_enable();
rkclk_configure_crypto(148500*KHz);
diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c
index c0a2ed002e..ad679e59b9 100644
--- a/src/soc/rockchip/rk3288/soc.c
+++ b/src/soc/rockchip/rk3288/soc.c
@@ -34,7 +34,7 @@ static void soc_init(struct device *dev)
ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB));
if (display_init_required())
rk_display_init(dev, (uintptr_t)_framebuffer,
- _framebuffer_size);
+ REGION_SIZE(framebuffer));
else
printk(BIOS_INFO, "Skipping display init.\n");
}