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-rw-r--r--src/soc/rockchip/rk3288/clock.c2
-rw-r--r--src/soc/rockchip/rk3288/include/soc/clock.h1
2 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index b6bafe81ae..1d163bf38d 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -78,10 +78,12 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
/* See linux/drivers/clk/rockchip/clk-rk3288.c for more APLL combinations */
static const struct pll_div apll_1800_cfg = PLL_DIVISORS(1800*MHz, 1, 1);
+static const struct pll_div apll_1416_cfg = PLL_DIVISORS(1416*MHz, 1, 1);
static const struct pll_div apll_1392_cfg = PLL_DIVISORS(1392*MHz, 1, 1);
static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2);
static const struct pll_div *apll_cfgs[] = {
[APLL_1800_MHZ] = &apll_1800_cfg,
+ [APLL_1416_MHZ] = &apll_1416_cfg,
[APLL_1392_MHZ] = &apll_1392_cfg,
[APLL_600_MHZ] = &apll_600_cfg,
};
diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h
index 995f4e51c2..39842a176c 100644
--- a/src/soc/rockchip/rk3288/include/soc/clock.h
+++ b/src/soc/rockchip/rk3288/include/soc/clock.h
@@ -30,6 +30,7 @@
enum apll_frequencies {
APLL_1800_MHZ,
+ APLL_1416_MHZ,
APLL_1392_MHZ,
APLL_600_MHZ,
};