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Diffstat (limited to 'src/soc/rockchip/rk3399/clock.c')
-rw-r--r--src/soc/rockchip/rk3399/clock.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 46c7a39006..53c6e30e5b 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -159,6 +159,13 @@ enum {
CLK_SARADC_DIV_CON_MASK = 0xff,
CLK_SARADC_DIV_CON_SHIFT = 8,
+ /* CLKSEL_CON27 */
+ CLK_TSADC_SEL_X24M = 0x0,
+ CLK_TSADC_SEL_MASK = 1,
+ CLK_TSADC_SEL_SHIFT = 15,
+ CLK_TSADC_DIV_CON_MASK = 0x3ff,
+ CLK_TSADC_DIV_CON_SHIFT = 0,
+
/* CLKSEL_CON47 & CLKSEL_CON48 */
ACLK_VOP_PLL_SEL_MASK = 0x3,
ACLK_VOP_PLL_SEL_SHIFT = 6,
@@ -714,3 +721,18 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz)
return 0;
}
+
+void rkclk_configure_tsadc(unsigned int hz)
+{
+ int src_clk_div;
+
+ /* use 24M as src clock */
+ src_clk_div = OSC_HZ / hz;
+ assert((src_clk_div - 1 < 1024) && (src_clk_div * hz == OSC_HZ));
+
+ write32(&cru_ptr->clksel_con[27], RK_CLRSETBITS(
+ CLK_TSADC_DIV_CON_MASK << CLK_TSADC_DIV_CON_SHIFT |
+ CLK_TSADC_SEL_MASK << CLK_TSADC_SEL_SHIFT,
+ src_clk_div << CLK_TSADC_DIV_CON_SHIFT |
+ CLK_TSADC_SEL_X24M << CLK_TSADC_SEL_SHIFT));
+}