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Diffstat (limited to 'src/soc/rockchip/rk3399/clock.c')
-rw-r--r--src/soc/rockchip/rk3399/clock.c40
1 files changed, 23 insertions, 17 deletions
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 9ac1ffedff..ded0a94008 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -494,26 +494,32 @@ void rkclk_init(void)
HCLK_PERILP1_PLL_SEL_SHIFT));
}
-void rkclk_configure_cpu(enum apll_frequencies apll_freq, bool is_big)
+void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster)
{
- u32 aclkm_div;
- u32 pclk_dbg_div;
- u32 atclk_div;
- u32 apll_l_hz;
- int con_base = is_big ? 2 : 0;
- int parent = is_big ? CLK_CORE_PLL_SEL_ABPLL : CLK_CORE_PLL_SEL_ALPLL;
- u32 *pll_con = is_big ? &cru_ptr->apll_b_con[0] :
- &cru_ptr->apll_l_con[0];
-
- apll_l_hz = apll_cfgs[apll_freq]->freq;
-
- rkclk_set_pll(pll_con, apll_cfgs[apll_freq]);
-
- aclkm_div = div_round_up(apll_l_hz, ACLKM_CORE_HZ) - 1;
+ u32 aclkm_div, atclk_div, pclk_dbg_div, apll_hz;
+ int con_base, parent;
+ u32 *pll_con;
+
+ switch (cluster) {
+ case CPU_CLUSTER_LITTLE:
+ con_base = 0;
+ parent = CLK_CORE_PLL_SEL_ALPLL;
+ pll_con = &cru_ptr->apll_l_con[0];
+ break;
+ case CPU_CLUSTER_BIG:
+ default:
+ con_base = 2;
+ parent = CLK_CORE_PLL_SEL_ABPLL;
+ pll_con = &cru_ptr->apll_b_con[0];
+ break;
+ }
- pclk_dbg_div = div_round_up(apll_l_hz, PCLK_DBG_HZ) - 1;
+ apll_hz = apll_cfgs[freq]->freq;
+ rkclk_set_pll(pll_con, apll_cfgs[freq]);
- atclk_div = div_round_up(apll_l_hz, ATCLK_CORE_HZ) - 1;
+ aclkm_div = div_round_up(apll_hz, ACLKM_CORE_HZ) - 1;
+ pclk_dbg_div = div_round_up(apll_hz, PCLK_DBG_HZ) - 1;
+ atclk_div = div_round_up(apll_hz, ATCLK_CORE_HZ) - 1;
write32(&cru_ptr->clksel_con[con_base],
RK_CLRSETBITS(ACLKM_CORE_DIV_CON_MASK <<