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Diffstat (limited to 'src/soc/rockchip/rk3399/clock.c')
-rw-r--r--src/soc/rockchip/rk3399/clock.c25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 383a761d60..eb413a1329 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -181,6 +181,13 @@ enum {
CLK_TSADC_DIV_CON_MASK = 0x3ff,
CLK_TSADC_DIV_CON_SHIFT = 0,
+ /* CLKSEL_CON44 */
+ CLK_PCLK_EDP_PLL_SEL_MASK = 1,
+ CLK_PCLK_EDP_PLL_SEL_SHIFT = 15,
+ CLK_PCLK_EDP_PLL_SEL_CPLL = 0,
+ CLK_PCLK_EDP_DIV_CON_MASK = 0x3f,
+ CLK_PCLK_EDP_DIV_CON_SHIFT = 8,
+
/* CLKSEL_CON47 & CLKSEL_CON48 */
ACLK_VOP_PLL_SEL_MASK = 0x3,
ACLK_VOP_PLL_SEL_SHIFT = 6,
@@ -838,3 +845,21 @@ int rkclk_was_watchdog_reset(void)
/* Bits 5 and 4 are "second" and "first" global watchdog reset. */
return read32(&cru_ptr->glb_rst_st) & 0x30;
}
+
+void rkclk_configure_edp(unsigned int hz)
+{
+ int src_clk_div;
+
+ src_clk_div = CPLL_HZ / hz;
+ assert((src_clk_div - 1 <= 63) && (src_clk_div * hz == CPLL_HZ));
+
+ write32(&cru_ptr->clksel_con[44],
+ RK_CLRSETBITS(CLK_PCLK_EDP_PLL_SEL_MASK <<
+ CLK_PCLK_EDP_PLL_SEL_SHIFT |
+ CLK_PCLK_EDP_DIV_CON_MASK <<
+ CLK_PCLK_EDP_DIV_CON_SHIFT,
+ CLK_PCLK_EDP_PLL_SEL_CPLL <<
+ CLK_PCLK_EDP_PLL_SEL_SHIFT |
+ (src_clk_div - 1) <<
+ CLK_PCLK_EDP_DIV_CON_SHIFT));
+}