3 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 428a210e00..3eeda3863e 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -834,3 +834,9 @@ void rkclk_configure_emmc(void)
 			      CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 			      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT));
 }
+
+int rkclk_was_watchdog_reset(void)
+{
+	/* Bits 5 and 4 are "second" and "first" global watchdog reset. */
+	return read32(&cru_ptr->glb_rst_st) & 0x30;
+}
diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h
index de86ed42a9..53f16ac2a6 100644
--- a/src/soc/rockchip/rk3399/include/soc/clock.h
+++ b/src/soc/rockchip/rk3399/include/soc/clock.h
@@ -112,6 +112,7 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz);
 void rkclk_configure_tsadc(unsigned int hz);
 void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz);
 void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
+int rkclk_was_watchdog_reset(void);
 uint32_t rkclk_i2c_clock_for_bus(unsigned bus);
 
 #endif	/* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index ec12c80e5f..54cfbe1135 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -24,6 +24,11 @@ SECTIONS
 	DMA_COHERENT(0x10000000, 2M)
 	FRAMEBUFFER(0x10200000, 8M)
 
+	/* 8K of special SRAM in PMU power domain. */
+	SYMBOL(pmu_sram, 0xFF3B0000)
+	WATCHDOG_TOMBSTONE(0xFF3B1FFC, 4)
+	SYMBOL(epmu_sram, 0xFF3B2000)
+
 	SRAM_START(0xFF8C0000)
 	PRERAM_CBMEM_CONSOLE(0xFF8C0000, 7K)
 	TIMESTAMP(0xFF8C1C00, 1K)