diff options
Diffstat (limited to 'src/soc/samsung/exynos5250/dmc_init_ddr3.c')
| -rw-r--r-- | src/soc/samsung/exynos5250/dmc_init_ddr3.c | 129 |
1 files changed, 64 insertions, 65 deletions
diff --git a/src/soc/samsung/exynos5250/dmc_init_ddr3.c b/src/soc/samsung/exynos5250/dmc_init_ddr3.c index 3b26c206c1..5a3cf3ef06 100644 --- a/src/soc/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5250/dmc_init_ddr3.c @@ -31,8 +31,10 @@ static void reset_phy_ctrl(void) { - writel(LPDDR3PHY_CTRL_PHY_RESET_ENABLE, &exynos_clock->lpddr3phy_ctrl); - writel(LPDDR3PHY_CTRL_PHY_RESET_DISABLE, &exynos_clock->lpddr3phy_ctrl); + write32(&exynos_clock->lpddr3phy_ctrl, + LPDDR3PHY_CTRL_PHY_RESET_ENABLE); + write32(&exynos_clock->lpddr3phy_ctrl, + LPDDR3PHY_CTRL_PHY_RESET_DISABLE); #if 0 /* @@ -65,14 +67,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, (mem->impedance << CA_CKE_DRVR_DS_OFFSET) | (mem->impedance << CA_CS_DRVR_DS_OFFSET) | (mem->impedance << CA_ADR_DRVR_DS_OFFSET); - writel(val, &exynos_phy0_control->phy_con39); - writel(val, &exynos_phy1_control->phy_con39); + write32(&exynos_phy0_control->phy_con39, val); + write32(&exynos_phy1_control->phy_con39, val); /* Set Read Latency and Burst Length for PHY0 and PHY1 */ val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); - writel(val, &exynos_phy0_control->phy_con42); - writel(val, &exynos_phy1_control->phy_con42); + write32(&exynos_phy0_control->phy_con42, val); + write32(&exynos_phy1_control->phy_con42, val); /* ZQ Calibration */ if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control)){ @@ -81,71 +83,69 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, } /* DQ Signal */ - writel(mem->phy0_pulld_dqs, &exynos_phy0_control->phy_con14); - writel(mem->phy1_pulld_dqs, &exynos_phy1_control->phy_con14); + write32(&exynos_phy0_control->phy_con14, mem->phy0_pulld_dqs); + write32(&exynos_phy1_control->phy_con14, mem->phy1_pulld_dqs); - writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) - | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT), - &exynos_dmc->concontrol); + write32(&exynos_dmc->concontrol, + mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT)); update_reset_dll(exynos_dmc, DDR_MODE_DDR3); /* DQS Signal */ - writel(mem->phy0_dqs, &exynos_phy0_control->phy_con4); - writel(mem->phy1_dqs, &exynos_phy1_control->phy_con4); + write32(&exynos_phy0_control->phy_con4, mem->phy0_dqs); + write32(&exynos_phy1_control->phy_con4, mem->phy1_dqs); - writel(mem->phy0_dq, &exynos_phy0_control->phy_con6); - writel(mem->phy1_dq, &exynos_phy1_control->phy_con6); + write32(&exynos_phy0_control->phy_con6, mem->phy0_dq); + write32(&exynos_phy1_control->phy_con6, mem->phy1_dq); - writel(mem->phy0_tFS, &exynos_phy0_control->phy_con10); - writel(mem->phy1_tFS, &exynos_phy1_control->phy_con10); + write32(&exynos_phy0_control->phy_con10, mem->phy0_tFS); + write32(&exynos_phy1_control->phy_con10, mem->phy1_tFS); val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) | (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); - writel(val, &exynos_phy0_control->phy_con12); - writel(val, &exynos_phy1_control->phy_con12); + write32(&exynos_phy0_control->phy_con12, val); + write32(&exynos_phy1_control->phy_con12, val); /* Start DLL locking */ - writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), - &exynos_phy0_control->phy_con12); - writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), - &exynos_phy1_control->phy_con12); + write32(&exynos_phy0_control->phy_con12, + val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT)); + write32(&exynos_phy1_control->phy_con12, + val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT)); update_reset_dll(exynos_dmc, DDR_MODE_DDR3); - writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT), - &exynos_dmc->concontrol); + write32(&exynos_dmc->concontrol, + mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)); /* Memory Channel Inteleaving Size */ - writel(mem->iv_size, &exynos_dmc->ivcontrol); + write32(&exynos_dmc->ivcontrol, mem->iv_size); /* Set DMC MEMCONTROL register */ val = mem->memcontrol & ~DMC_MEMCONTROL_DSREF_ENABLE; - writel(val, &exynos_dmc->memcontrol); + write32(&exynos_dmc->memcontrol, val); - writel(mem->memconfig, &exynos_dmc->memconfig0); - writel(mem->memconfig, &exynos_dmc->memconfig1); - writel(mem->membaseconfig0, &exynos_dmc->membaseconfig0); - writel(mem->membaseconfig1, &exynos_dmc->membaseconfig1); + write32(&exynos_dmc->memconfig0, mem->memconfig); + write32(&exynos_dmc->memconfig1, mem->memconfig); + write32(&exynos_dmc->membaseconfig0, mem->membaseconfig0); + write32(&exynos_dmc->membaseconfig1, mem->membaseconfig1); /* Precharge Configuration */ - writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT, - &exynos_dmc->prechconfig); + write32(&exynos_dmc->prechconfig, + mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT); /* Power Down mode Configuration */ - writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | - mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT, - &exynos_dmc->pwrdnconfig); + write32(&exynos_dmc->pwrdnconfig, + mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT); /* TimingRow, TimingData, TimingPower and Timingaref * values as per Memory AC parameters */ - writel(mem->timing_ref, &exynos_dmc->timingref); - writel(mem->timing_row, &exynos_dmc->timingrow); - writel(mem->timing_data, &exynos_dmc->timingdata); - writel(mem->timing_power, &exynos_dmc->timingpower); + write32(&exynos_dmc->timingref, mem->timing_ref); + write32(&exynos_dmc->timingrow, mem->timing_row); + write32(&exynos_dmc->timingdata, mem->timing_data); + write32(&exynos_dmc->timingpower, mem->timing_power); /* Send PALL command */ dmc_config_prech(mem, exynos_dmc); @@ -162,19 +162,19 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, if (mem->gate_leveling_enable) { val = PHY_CON0_RESET_VAL; val |= P0_CMD_EN; - writel(val, &exynos_phy0_control->phy_con0); - writel(val, &exynos_phy1_control->phy_con0); + write32(&exynos_phy0_control->phy_con0, val); + write32(&exynos_phy1_control->phy_con0, val); val = PHY_CON2_RESET_VAL; val |= INIT_DESKEW_EN; - writel(val, &exynos_phy0_control->phy_con2); - writel(val, &exynos_phy1_control->phy_con2); + write32(&exynos_phy0_control->phy_con2, val); + write32(&exynos_phy1_control->phy_con2, val); val = PHY_CON0_RESET_VAL; val |= P0_CMD_EN; val |= BYTE_RDLVL_EN; - writel(val, &exynos_phy0_control->phy_con0); - writel(val, &exynos_phy1_control->phy_con0); + write32(&exynos_phy0_control->phy_con0, val); + write32(&exynos_phy1_control->phy_con0, val); val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | @@ -182,30 +182,30 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); - writel(val, &exynos_phy0_control->phy_con12); - writel(val, &exynos_phy1_control->phy_con12); + write32(&exynos_phy0_control->phy_con12, val); + write32(&exynos_phy1_control->phy_con12, val); val = PHY_CON2_RESET_VAL; val |= INIT_DESKEW_EN; val |= RDLVL_GATE_EN; - writel(val, &exynos_phy0_control->phy_con2); - writel(val, &exynos_phy1_control->phy_con2); + write32(&exynos_phy0_control->phy_con2, val); + write32(&exynos_phy1_control->phy_con2, val); val = PHY_CON0_RESET_VAL; val |= P0_CMD_EN; val |= BYTE_RDLVL_EN; val |= CTRL_SHGATE; - writel(val, &exynos_phy0_control->phy_con0); - writel(val, &exynos_phy1_control->phy_con0); + write32(&exynos_phy0_control->phy_con0, val); + write32(&exynos_phy1_control->phy_con0, val); val = PHY_CON1_RESET_VAL; val &= ~(CTRL_GATEDURADJ_MASK); - writel(val, &exynos_phy0_control->phy_con1); - writel(val, &exynos_phy1_control->phy_con1); + write32(&exynos_phy0_control->phy_con1, val); + write32(&exynos_phy1_control->phy_con1, val); - writel(CTRL_RDLVL_GATE_ENABLE, &exynos_dmc->rdlvl_config); + write32(&exynos_dmc->rdlvl_config, CTRL_RDLVL_GATE_ENABLE); i = RDLVL_COMPLETE_TIMEOUT; - while ((readl(&exynos_dmc->phystatus) & + while ((read32(&exynos_dmc->phystatus) & (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) != (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) { /* @@ -219,10 +219,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, printk(BIOS_EMERG, "Timeout on RDLVL. No DRAM.\n"); return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; } - writel(CTRL_RDLVL_GATE_DISABLE, &exynos_dmc->rdlvl_config); + write32(&exynos_dmc->rdlvl_config, CTRL_RDLVL_GATE_DISABLE); - writel(0, &exynos_phy0_control->phy_con14); - writel(0, &exynos_phy1_control->phy_con14); + write32(&exynos_phy0_control->phy_con14, 0); + write32(&exynos_phy1_control->phy_con14, 0); val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | @@ -231,8 +231,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) | (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) | (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT); - writel(val, &exynos_phy0_control->phy_con12); - writel(val, &exynos_phy1_control->phy_con12); + write32(&exynos_phy0_control->phy_con12, val); + write32(&exynos_phy1_control->phy_con12, val); update_reset_dll(exynos_dmc, DDR_MODE_DDR3); } @@ -240,11 +240,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, /* Send PALL command */ dmc_config_prech(mem, exynos_dmc); - writel(mem->memcontrol, &exynos_dmc->memcontrol); + write32(&exynos_dmc->memcontrol, mem->memcontrol); /* Set DMC Concontrol and enable auto-refresh counter */ - writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) - | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), - &exynos_dmc->concontrol); + write32(&exynos_dmc->concontrol, + mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT)); return 0; } |