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Diffstat (limited to 'src/soc/samsung/exynos5420/usb.c')
-rw-r--r--src/soc/samsung/exynos5420/usb.c69
1 files changed, 20 insertions, 49 deletions
diff --git a/src/soc/samsung/exynos5420/usb.c b/src/soc/samsung/exynos5420/usb.c
index 0df63e2666..9313fea147 100644
--- a/src/soc/samsung/exynos5420/usb.c
+++ b/src/soc/samsung/exynos5420/usb.c
@@ -57,23 +57,13 @@ static void setup_dwc3(struct exynos5_usb_drd_dwc3 *dwc3)
/* Set relevant registers to default values (clearing all reset bits) */
- writel(0x1 << 24 | /* activate PHY low power states */
- 0x4 << 19 | /* low power delay value */
- 0x1 << 18 | /* activate PHY low power delay */
- 0x1 << 17 | /* enable SuperSpeed PHY suspend */
- 0x1 << 1 | /* default Tx deemphasis value */
- 0, &dwc3->usb3pipectl);
+ write32(&dwc3->usb3pipectl,
+ 0x1 << 24 | 0x4 << 19 | 0x1 << 18 | 0x1 << 17 | 0x1 << 1 | 0);
/* Configure PHY clock turnaround for 8-bit UTMI+, disable suspend */
- writel(0x9 << 10 | /* PHY clock turnaround for 8-bit UTMI+ */
- 0x1 << 8 | /* enable PHY sleep in L1 */
- 0x1 << 6 | /* enable PHY suspend */
- 0, &dwc3->usb2phycfg);
-
- writel(0x5dc << 19 | /* suspend clock scale for 24MHz */
- 0x1 << 16 | /* retry SS three times (bugfix from U-Boot) */
- 0x1 << 12 | /* port capability HOST */
- 0, &dwc3->ctl);
+ write32(&dwc3->usb2phycfg, 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0);
+
+ write32(&dwc3->ctl, 0x5dc << 19 | 0x1 << 16 | 0x1 << 12 | 0);
}
void setup_usb_drd0_dwc3()
@@ -96,44 +86,25 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy)
setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1);
/* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */
- writel(1 << 6, &phy->utmi);
-
- writel(0x88 << 23 | /* spread spectrum refclk selector */
- 0x1 << 20 | /* enable spread spectrum */
- 0x1 << 19 | /* enable prescaler refclk */
- 0x68 << 11 | /* multiplier for 24MHz refclk */
- 0x5 << 5 | /* select 24MHz refclk (weird, from U-Boot) */
- 0x1 << 4 | /* power supply in normal operating mode */
- 0x3 << 2 | /* use external refclk (undocumented on 5420?)*/
- 0x1 << 1 | /* force port reset */
- 0x1 << 0 | /* normal operating mode */
- 0, &phy->clkrst);
-
- writel(0x9 << 26 | /* LOS level */
- 0x3 << 22 | /* TX VREF tune */
- 0x1 << 20 | /* TX rise tune */
- 0x1 << 18 | /* TX res tune */
- 0x3 << 13 | /* TX HS X Vtune */
- 0x3 << 9 | /* TX FS/LS tune */
- 0x3 << 6 | /* SQRX tune */
- 0x4 << 3 | /* OTG tune */
- 0x4 << 0 | /* comp disc tune */
- 0, &phy->param0);
-
- writel(0x7f << 19 | /* reserved */
- 0x7f << 12 | /* Tx launch amplitude */
- 0x20 << 6 | /* Tx deemphasis 6dB */
- 0x1c << 0 | /* Tx deemphasis 3.5dB (value from U-Boot) */
- 0, &phy->param1);
+ write32(&phy->utmi, 1 << 6);
+
+ write32(&phy->clkrst,
+ 0x88 << 23 | 0x1 << 20 | 0x1 << 19 | 0x68 << 11 | 0x5 << 5 | 0x1 << 4 | 0x3 << 2 | 0x1 << 1 | 0x1 << 0 | 0);
+
+ write32(&phy->param0,
+ 0x9 << 26 | 0x3 << 22 | 0x1 << 20 | 0x1 << 18 | 0x3 << 13 | 0x3 << 9 | 0x3 << 6 | 0x4 << 3 | 0x4 << 0 | 0);
+
+ write32(&phy->param1,
+ 0x7f << 19 | 0x7f << 12 | 0x20 << 6 | 0x1c << 0 | 0);
/* disable all test features */
- writel(0, &phy->test);
+ write32(&phy->test, 0);
/* UTMI clock select? ("must be 0x1") */
- writel(0x1 << 2, &phy->utmiclksel);
+ write32(&phy->utmiclksel, 0x1 << 2);
/* Samsung magic, undocumented (from U-Boot) */
- writel(0x0, &phy->resume);
+ write32(&phy->resume, 0x0);
udelay(10);
clrbits_le32(&phy->clkrst, 0x1 << 1); /* deassert port reset */
@@ -163,7 +134,7 @@ void setup_usb_host_phy(int hsic_gpio)
printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n",
hsic_gpio ? "with" : "without");
- hostphy_ctrl0 = readl(&exynos_usb_host_phy->usbphyctrl0);
+ hostphy_ctrl0 = read32(&exynos_usb_host_phy->usbphyctrl0);
hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK |
HOST_CTRL0_COMMONON_N |
/* HOST Phy setting */
@@ -177,7 +148,7 @@ void setup_usb_host_phy(int hsic_gpio)
/* HOST Phy setting */
HOST_CTRL0_LINKSWRST |
HOST_CTRL0_UTMISWRST);
- writel(hostphy_ctrl0, &exynos_usb_host_phy->usbphyctrl0);
+ write32(&exynos_usb_host_phy->usbphyctrl0, hostphy_ctrl0);
udelay(10);
clrbits_le32(&exynos_usb_host_phy->usbphyctrl0,
HOST_CTRL0_LINKSWRST |