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-rw-r--r--src/soc/samsung/exynos5250/clock.c2
-rw-r--r--src/soc/samsung/exynos5420/clock.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c
index 63e30f6749..a6cc3c78b9 100644
--- a/src/soc/samsung/exynos5250/clock.c
+++ b/src/soc/samsung/exynos5250/clock.c
@@ -617,7 +617,7 @@ int clock_epll_set_rate(unsigned long rate)
epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
/*
- * Required period ( in cycles) to generate a stable clock output.
+ * Required period (in cycles) to generate a stable clock output.
* The maximum clock time can be up to 3000 * PDIV cycles of PLLs
* frequency input (as per spec)
*/
diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c
index 3c4bb04794..04125d9cb1 100644
--- a/src/soc/samsung/exynos5420/clock.c
+++ b/src/soc/samsung/exynos5420/clock.c
@@ -582,7 +582,7 @@ int clock_epll_set_rate(unsigned long rate)
epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
/*
- * Required period ( in cycles) to generate a stable clock output.
+ * Required period (in cycles) to generate a stable clock output.
* The maximum clock time can be up to 3000 * PDIV cycles of PLLs
* frequency input (as per spec)
*/