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-rw-r--r--src/soc/intel/baytrail/romstage/raminit.c4
-rw-r--r--src/soc/intel/broadwell/igd.c3
-rw-r--r--src/soc/intel/broadwell/romstage/raminit.c2
-rw-r--r--src/soc/intel/common/mrc_cache.c2
-rw-r--r--src/soc/intel/skylake/igd.c3
-rw-r--r--src/soc/intel/skylake/romstage/romstage.c2
6 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index d45b9eab26..a79fe9533b 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -16,7 +16,6 @@
#include <stddef.h>
#include <arch/acpi.h>
#include <arch/io.h>
-#include <bootmode.h>
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
@@ -31,6 +30,7 @@
#include <soc/romstage.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
+#include <vboot/vboot_common.h>
static void reset_system(void)
{
@@ -123,7 +123,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
if (!mp->io_hole_mb)
mp->io_hole_mb = 2048;
- if (recovery_mode_enabled()) {
+ if (vboot_recovery_mode_enabled()) {
printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n");
} else if (!mrc_cache_get_current(&cache)) {
mp->saved_data_size = cache->size;
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index d25ddcc547..ccb1e93604 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -487,8 +487,7 @@ static void igd_init(struct device *dev)
/* Wait for any configured pre-graphics delay */
if (!acpi_is_wakeup_s3()) {
#if IS_ENABLED(CONFIG_CHROMEOS)
- if (developer_mode_enabled() || recovery_mode_enabled() ||
- vboot_wants_oprom())
+ if (display_init_required() || vboot_wants_oprom())
mdelay(CONFIG_PRE_GRAPHICS_DELAY);
#else
mdelay(CONFIG_PRE_GRAPHICS_DELAY);
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 488b231a96..61b1bc9cb9 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -48,7 +48,7 @@ void raminit(struct pei_data *pei_data)
broadwell_fill_pei_data(pei_data);
- if (recovery_mode_enabled()) {
+ if (vboot_recovery_mode_enabled()) {
/* Recovery mode does not use MRC cache */
printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n");
} else if (!mrc_cache_get_current(&cache)) {
diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c
index cf819cfdcf..c123da9dc7 100644
--- a/src/soc/intel/common/mrc_cache.c
+++ b/src/soc/intel/common/mrc_cache.c
@@ -19,6 +19,8 @@
#include <cbmem.h>
#include <fmap.h>
#include <ip_checksum.h>
+#include <vboot/vboot_common.h>
+
#include "mrc_cache.h"
#include "nvm.h"
diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index 209d22c8cf..3e29ab0ffd 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -91,8 +91,7 @@ static void igd_init(struct device *dev)
/* Wait for any configured pre-graphics delay */
if (!acpi_is_wakeup_s3()) {
#if IS_ENABLED(CONFIG_CHROMEOS)
- if (developer_mode_enabled() || recovery_mode_enabled() ||
- vboot_wants_oprom())
+ if (display_init_required() || vboot_wants_oprom())
mdelay(CONFIG_PRE_GRAPHICS_DELAY);
#else
mdelay(CONFIG_PRE_GRAPHICS_DELAY);
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 8375ccde76..b16e5aa22c 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -100,7 +100,7 @@ void soc_memory_init_params(struct romstage_params *params,
upd->IedSize = CONFIG_IED_REGION_SIZE;
upd->ProbelessTrace = config->ProbelessTrace;
upd->EnableTraceHub = config->EnableTraceHub;
- if (recovery_mode_enabled())
+ if (vboot_recovery_mode_enabled())
upd->SaGv = 0; /* Disable SaGv in recovery mode. */
else
upd->SaGv = config->SaGv;