8 files changed, 12 insertions, 12 deletions
diff --git a/src/soc/broadcom/cygnus/ns16550.c b/src/soc/broadcom/cygnus/ns16550.c
index e7008274f6..68c4715cb3 100644
--- a/src/soc/broadcom/cygnus/ns16550.c
+++ b/src/soc/broadcom/cygnus/ns16550.c
@@ -120,7 +120,7 @@ void uart_fill_lb(void *data)
 	struct lb_serial serial;
 	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
 	serial.baseaddr = (uintptr_t)regs;
-	serial.baud = CONFIG_TTYS0_BAUD;
+	serial.baud = get_uart_baudrate();
 	serial.regwidth = 4;
 	lb_add_serial(&serial, data);
 
diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c
index df1a5ace04..f610f6a05d 100644
--- a/src/soc/imgtec/pistachio/uart.c
+++ b/src/soc/imgtec/pistachio/uart.c
@@ -124,7 +124,7 @@ void uart_init(int idx)
 		return;
 
 	unsigned int div;
-	div = uart_baudrate_divisor(CONFIG_TTYS0_BAUD,
+	div = uart_baudrate_divisor(get_uart_baudrate(),
 				    uart_platform_refclk(), 16);
 	uart8250_mem_init(base, div);
 }
@@ -150,7 +150,7 @@ void uart_fill_lb(void *data)
 	struct lb_serial serial;
 	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
 	serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
-	serial.baud = CONFIG_TTYS0_BAUD;
+	serial.baud = get_uart_baudrate();
 	serial.regwidth = 1 << UART_SHIFT;
 	lb_add_serial(&serial, data);
 
diff --git a/src/soc/mediatek/mt8173/uart.c b/src/soc/mediatek/mt8173/uart.c
index 36a279fa65..93625c4bfb 100644
--- a/src/soc/mediatek/mt8173/uart.c
+++ b/src/soc/mediatek/mt8173/uart.c
@@ -87,7 +87,7 @@ static void mtk_uart_init(void)
 {
 	/* Use a hardcoded divisor for now. */
 	const unsigned uartclk = 26 * MHz;
-	const unsigned baudrate = CONFIG_TTYS0_BAUD;
+	const unsigned baudrate = get_uart_baudrate();
 	const uint8_t line_config = UART8250_LCR_WLS_8;	/* 8n1 */
 	unsigned highspeed, quot, divisor, remainder;
 
@@ -177,7 +177,7 @@ void uart_fill_lb(void *data)
 	struct lb_serial serial;
 	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
 	serial.baseaddr = UART0_BASE;
-	serial.baud = CONFIG_TTYS0_BAUD;
+	serial.baud = get_uart_baudrate();
 	serial.regwidth = 4;
 	lb_add_serial(&serial, data);
 
diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c
index 0d5233788d..5cb8112d81 100644
--- a/src/soc/nvidia/tegra124/uart.c
+++ b/src/soc/nvidia/tegra124/uart.c
@@ -136,7 +136,7 @@ void uart_fill_lb(void *data)
 	struct lb_serial serial;
 	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
 	serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
-	serial.baud = CONFIG_TTYS0_BAUD;
+	serial.baud = get_uart_baudrate();
 	serial.regwidth = 4;
 	lb_add_serial(&serial, data);
 
diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c
index 1c52687491..97dc740ebf 100644
--- a/src/soc/nvidia/tegra210/uart.c
+++ b/src/soc/nvidia/tegra210/uart.c
@@ -123,7 +123,7 @@ void uart_fill_lb(void *data)
 	struct lb_serial serial;
 	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
 	serial.baseaddr = CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS;
-	serial.baud = CONFIG_TTYS0_BAUD;
+	serial.baud = get_uart_baudrate();
 	serial.regwidth = 4;
 	lb_add_serial(&serial, data);
 
diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c
index 671a6d1281..4b0bffd216 100644
--- a/src/soc/qualcomm/ipq40xx/uart.c
+++ b/src/soc/qualcomm/ipq40xx/uart.c
@@ -297,7 +297,7 @@ void uart_fill_lb(void *data)
 
 	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
 	serial.baseaddr = (uint32_t)UART1_DM_BASE;
-	serial.baud = CONFIG_TTYS0_BAUD;
+	serial.baud = get_uart_baudrate();
 	serial.regwidth = 1;
 
 	lb_add_serial(&serial, data);
diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c
index 7ad6cbe6d9..78c72804c9 100644
--- a/src/soc/samsung/exynos5250/uart.c
+++ b/src/soc/samsung/exynos5250/uart.c
@@ -61,7 +61,7 @@ static void serial_setbrg_dev(struct s5p_uart *uart)
 
 	// All UARTs share the same clock.
 	uclk = clock_get_periph_rate(PERIPH_ID_UART3);
-	val = uclk / CONFIG_TTYS0_BAUD;
+	val = uclk / get_uart_baudrate();
 
 	write32(&uart->ubrdiv, val / 16 - 1);
 
@@ -191,7 +191,7 @@ void uart_fill_lb(void *data)
 	struct lb_serial serial;
 	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
 	serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
-	serial.baud = CONFIG_TTYS0_BAUD;
+	serial.baud = get_uart_baudrate();
 	serial.regwidth = 4;
 	lb_add_serial(&serial, data);
 
diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c
index a38be07d13..146151ee5b 100644
--- a/src/soc/samsung/exynos5420/uart.c
+++ b/src/soc/samsung/exynos5420/uart.c
@@ -61,7 +61,7 @@ static void serial_setbrg_dev(struct s5p_uart *uart)
 
 	// All UARTs share the same clock.
 	uclk = clock_get_periph_rate(PERIPH_ID_UART3);
-	val = uclk / CONFIG_TTYS0_BAUD;
+	val = uclk / get_uart_baudrate();
 
 	write32(&uart->ubrdiv, val / 16 - 1);
 
@@ -182,7 +182,7 @@ void uart_fill_lb(void *data)
 	struct lb_serial serial;
 	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
 	serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
-	serial.baud = CONFIG_TTYS0_BAUD;
+	serial.baud = get_uart_baudrate();
 	serial.regwidth = 4;
 	serial.input_hertz = uart_platform_refclk();
 	serial.uart_pci_addr = 0;