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-rw-r--r--src/soc/intel/alderlake/acpi/gpio.asl2
-rw-r--r--src/soc/intel/alderlake/chip.c2
-rw-r--r--src/soc/intel/alderlake/include/soc/gpio.h6
-rw-r--r--src/soc/intel/apollolake/include/soc/gpio.h7
-rw-r--r--src/soc/intel/cannonlake/acpi/gpio.asl6
-rw-r--r--src/soc/intel/cannonlake/gpio_common.c2
-rw-r--r--src/soc/intel/cannonlake/include/soc/gpio.h5
-rw-r--r--src/soc/intel/common/acpi/gpio.asl4
-rw-r--r--src/soc/intel/common/acpi/platform.asl2
-rw-r--r--src/soc/intel/common/block/acpi/acpi/pep.asl2
-rw-r--r--src/soc/intel/common/block/gpio/gpio.c2
-rw-r--r--src/soc/intel/common/block/include/intelblocks/gpio.h8
-rw-r--r--src/soc/intel/denverton_ns/include/soc/gpio.h6
-rw-r--r--src/soc/intel/elkhartlake/chip.c2
-rw-r--r--src/soc/intel/elkhartlake/include/soc/gpio.h6
-rw-r--r--src/soc/intel/icelake/chip.c2
-rw-r--r--src/soc/intel/icelake/include/soc/gpio.h5
-rw-r--r--src/soc/intel/jasperlake/chip.c2
-rw-r--r--src/soc/intel/jasperlake/include/soc/gpio.h6
-rw-r--r--src/soc/intel/skylake/include/soc/gpio.h7
-rw-r--r--src/soc/intel/tigerlake/chip.c2
-rw-r--r--src/soc/intel/tigerlake/include/soc/gpio.h6
-rw-r--r--src/soc/intel/xeon_sp/include/soc/gpio.h6
23 files changed, 79 insertions, 19 deletions
diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl
index e21f6d5481..50d999f7f4 100644
--- a/src/soc/intel/alderlake/acpi/gpio.asl
+++ b/src/soc/intel/alderlake/acpi/gpio.asl
@@ -166,6 +166,6 @@ Method (EGPM, 0, Serialized)
/* Enable PM bits */
For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
{
- CGPM (Local0, MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ CGPM (Local0, MISCCFG_GPIO_PM_CONFIG_BITS)
}
}
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index 977705268b..dc54845600 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -119,7 +119,7 @@ static void soc_fill_gpio_pm_configuration(void)
memcpy(value, config->gpio_pm, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
else
- memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+ memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
gpio_pm_configure(value, TOTAL_GPIO_COMM);
diff --git a/src/soc/intel/alderlake/include/soc/gpio.h b/src/soc/intel/alderlake/include/soc/gpio.h
index eec698a1e7..acaade449d 100644
--- a/src/soc/intel/alderlake/include/soc/gpio.h
+++ b/src/soc/intel/alderlake/include/soc/gpio.h
@@ -9,4 +9,10 @@
#define CROS_GPIO_NAME "INTC1055"
#define CROS_GPIO_DEVICE_NAME "INTC1055:00"
+/* Enable GPIO community power management configuration */
+#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \
+ MISCCFG_GPPGCBDPCGEN | MISCCFG_GPSIDEDPCGEN | \
+ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
#endif
diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h
index 9b809c000a..f06b9f52dc 100644
--- a/src/soc/intel/apollolake/include/soc/gpio.h
+++ b/src/soc/intel/apollolake/include/soc/gpio.h
@@ -10,4 +10,11 @@
#endif
#include <intelblocks/gpio.h>/* intelblocks/gpio.h depends on definitions in
soc/gpio_glk.h and soc/gpio_apl.h */
+
+/*
+ * APL/GLK doesn't support dynamic GPIO PM hence GPIO community
+ * MISCCFG register doesn't have PM bits
+ */
+#define MISCCFG_GPIO_PM_CONFIG_BITS 0
+
#endif
diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl
index f1284e1412..7776acc553 100644
--- a/src/soc/intel/cannonlake/acpi/gpio.asl
+++ b/src/soc/intel/cannonlake/acpi/gpio.asl
@@ -138,9 +138,9 @@ Method (CGPM, 2, Serialized)
Store (GPID (Arg0), Local0)
If (LNotEqual (Local0, 0)) {
/* Mask off current PM bits */
- PCRA (Local0, GPIO_MISCCFG, Not (MISCCFG_ENABLE_GPIO_PM_CONFIG))
+ PCRA (Local0, GPIO_MISCCFG, Not (MISCCFG_GPIO_PM_CONFIG_BITS))
/* Mask in requested bits */
- PCRO (Local0, GPIO_MISCCFG, And (Arg1, MISCCFG_ENABLE_GPIO_PM_CONFIG))
+ PCRO (Local0, GPIO_MISCCFG, And (Arg1, MISCCFG_GPIO_PM_CONFIG_BITS))
}
}
@@ -181,6 +181,6 @@ Method (EGPM, 0, Serialized)
/* Enable PM bits */
For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
{
- CGPM (Local0, MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ CGPM (Local0, MISCCFG_GPIO_PM_CONFIG_BITS)
}
}
diff --git a/src/soc/intel/cannonlake/gpio_common.c b/src/soc/intel/cannonlake/gpio_common.c
index 45331ec822..21a5801648 100644
--- a/src/soc/intel/cannonlake/gpio_common.c
+++ b/src/soc/intel/cannonlake/gpio_common.c
@@ -17,7 +17,7 @@ void soc_gpio_pm_configuration(void)
memcpy(value, config->gpio_pm, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
else
- memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+ memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
gpio_pm_configure(value, TOTAL_GPIO_COMM);
diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h
index b39798e96d..9ffa8f1bc2 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio.h
@@ -12,6 +12,11 @@
#endif
#include <intelblocks/gpio.h>
+/* Enable GPIO community power management configuration */
+#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPSIDEDPCGEN | \
+ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
#ifndef __ACPI__
struct pad_config;
void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads);
diff --git a/src/soc/intel/common/acpi/gpio.asl b/src/soc/intel/common/acpi/gpio.asl
index dbfa7af980..225f72a46f 100644
--- a/src/soc/intel/common/acpi/gpio.asl
+++ b/src/soc/intel/common/acpi/gpio.asl
@@ -11,8 +11,8 @@ Method (CGPM, 2, Serialized)
Local0 = GPID (Arg0)
If (Local0 != 0) {
/* Mask off current PM bits */
- PCRA (Local0, GPIO_MISCCFG, ~MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ PCRA (Local0, GPIO_MISCCFG, ~MISCCFG_GPIO_PM_CONFIG_BITS)
/* Mask in requested bits */
- PCRO (Local0, GPIO_MISCCFG, Arg1 & MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ PCRO (Local0, GPIO_MISCCFG, Arg1 & MISCCFG_GPIO_PM_CONFIG_BITS)
}
}
diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl
index a973149e6d..496f184278 100644
--- a/src/soc/intel/common/acpi/platform.asl
+++ b/src/soc/intel/common/acpi/platform.asl
@@ -30,7 +30,7 @@ Method (_PTS, 1)
}
/*
* Save the current PM bits then
- * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG
+ * enable GPIO PM with MISCCFG_GPIO_PM_CONFIG_BITS
*/
If (CondRefOf (\_SB.PCI0.EGPM))
{
diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl
index b6a0d9d91a..2e2a25f279 100644
--- a/src/soc/intel/common/block/acpi/acpi/pep.asl
+++ b/src/soc/intel/common/block/acpi/acpi/pep.asl
@@ -91,7 +91,7 @@ Device(PEPD)
/*
* Save the current PM bits then
- * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG
+ * enable GPIO PM with MISCCFG_GPIO_PM_CONFIG_BITS
*/
If (CondRefOf (\_SB.PCI0.EGPM))
{
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
index c747f30c8a..417dfb88b2 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
+++ b/src/soc/intel/common/block/gpio/gpio.c
@@ -656,7 +656,7 @@ void gpio_pm_configure(const uint8_t *misccfg_pm_values, size_t num)
{
int i;
size_t gpio_communities;
- const uint8_t misccfg_pm_mask = (uint8_t)~MISCCFG_ENABLE_GPIO_PM_CONFIG;
+ const uint8_t misccfg_pm_mask = (uint8_t)~MISCCFG_GPIO_PM_CONFIG_BITS;
const struct pad_community *comm;
comm = soc_gpio_get_community(&gpio_communities);
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h
index 45ae1da4fd..3f79b19f94 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio.h
@@ -6,6 +6,10 @@
#include <soc/gpio.h>
#include "gpio_defs.h"
+/* GPIO community IOSF sideband VNNREQ/ACK handshake */
+#define MISCCFG_GPVNNREQEN (1 << 7)
+/* GPIO community PGCB clock gating */
+#define MISCCFG_GPPGCBDPCGEN (1 << 6)
/* GPIO community IOSF sideband clock gating */
#define MISCCFG_GPSIDEDPCGEN (1 << 5)
/* GPIO community RCOMP clock gating */
@@ -18,10 +22,6 @@
#define MISCCFG_GPDPCGEN (1 << 1)
/* GPIO community local clock gating */
#define MISCCFG_GPDLCGEN (1 << 0)
-/* Enable GPIO community power management configuration */
-#define MISCCFG_ENABLE_GPIO_PM_CONFIG (MISCCFG_GPSIDEDPCGEN | \
- MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
- | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
#ifndef __ACPI__
#include <types.h>
diff --git a/src/soc/intel/denverton_ns/include/soc/gpio.h b/src/soc/intel/denverton_ns/include/soc/gpio.h
index fcf57ff2e4..41438c20fb 100644
--- a/src/soc/intel/denverton_ns/include/soc/gpio.h
+++ b/src/soc/intel/denverton_ns/include/soc/gpio.h
@@ -33,4 +33,10 @@
#include <intelblocks/gpio.h>/* intelblocks/gpio.h depends on definitions in
lines above and soc/gpio_defs.h */
+/*
+ * DNV doesn't support dynamic GPIO PM hence GPIO community
+ * MISCCFG register doesn't have PM bits
+ */
+#define MISCCFG_GPIO_PM_CONFIG_BITS 0
+
#endif /* _SOC_DENVERTON_NS_GPIO_H_ */
diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c
index f1c75b6eac..b14edd6cc6 100644
--- a/src/soc/intel/elkhartlake/chip.c
+++ b/src/soc/intel/elkhartlake/chip.c
@@ -108,7 +108,7 @@ static void soc_fill_gpio_pm_configuration(void)
memcpy(value, config->gpio_pm, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
else
- memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+ memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
gpio_pm_configure(value, TOTAL_GPIO_COMM);
diff --git a/src/soc/intel/elkhartlake/include/soc/gpio.h b/src/soc/intel/elkhartlake/include/soc/gpio.h
index 367df82276..47f792caec 100644
--- a/src/soc/intel/elkhartlake/include/soc/gpio.h
+++ b/src/soc/intel/elkhartlake/include/soc/gpio.h
@@ -12,4 +12,10 @@
#define CROS_GPIO_COMM4_NAME "INT34C8:02"
#define CROS_GPIO_COMM5_NAME "INT34C8:03"
+/* Enable GPIO community power management configuration */
+#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \
+ MISCCFG_GPPGCBDPCGEN | MISCCFG_GPSIDEDPCGEN | \
+ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
#endif
diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c
index 134d7cf214..821a9e04ed 100644
--- a/src/soc/intel/icelake/chip.c
+++ b/src/soc/intel/icelake/chip.c
@@ -98,7 +98,7 @@ static void soc_fill_gpio_pm_configuration(void)
memcpy(value, config->gpio_pm, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
else
- memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+ memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
gpio_pm_configure(value, TOTAL_GPIO_COMM);
diff --git a/src/soc/intel/icelake/include/soc/gpio.h b/src/soc/intel/icelake/include/soc/gpio.h
index 3eae13f832..5d4269d637 100644
--- a/src/soc/intel/icelake/include/soc/gpio.h
+++ b/src/soc/intel/icelake/include/soc/gpio.h
@@ -8,4 +8,9 @@
#define CROS_GPIO_DEVICE_NAME "INT3455:00"
+/* Enable GPIO community power management configuration */
+#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPSIDEDPCGEN | \
+ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
#endif
diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c
index c663d1f5e7..1051fbc9ab 100644
--- a/src/soc/intel/jasperlake/chip.c
+++ b/src/soc/intel/jasperlake/chip.c
@@ -114,7 +114,7 @@ static void soc_fill_gpio_pm_configuration(void)
memcpy(value, config->gpio_pm, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
else
- memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+ memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
gpio_pm_configure(value, TOTAL_GPIO_COMM);
diff --git a/src/soc/intel/jasperlake/include/soc/gpio.h b/src/soc/intel/jasperlake/include/soc/gpio.h
index 384c0672d3..fa7f915eb0 100644
--- a/src/soc/intel/jasperlake/include/soc/gpio.h
+++ b/src/soc/intel/jasperlake/include/soc/gpio.h
@@ -12,4 +12,10 @@
#define CROS_GPIO_COMM4_NAME "INT34C8:02"
#define CROS_GPIO_COMM5_NAME "INT34C8:03"
+/* Enable GPIO community power management configuration */
+#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \
+ MISCCFG_GPPGCBDPCGEN | MISCCFG_GPSIDEDPCGEN | \
+ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
#endif
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index 283df83b11..b55dea8197 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -8,4 +8,11 @@
soc/gpio_defs.h */
#define CROS_GPIO_DEVICE_NAME "INT344B:00"
+
+/*
+ * SPT PCH doesn't support dynamic GPIO PM hence GPIO community
+ * MISCCFG register doesn't have PM bits
+ */
+#define MISCCFG_GPIO_PM_CONFIG_BITS 0
+
#endif
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index 024da1538d..2a0d7d0326 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -119,7 +119,7 @@ static void soc_fill_gpio_pm_configuration(void)
memcpy(value, config->gpio_pm, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
else
- memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+ memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
gpio_pm_configure(value, TOTAL_GPIO_COMM);
diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h
index b9842b90ef..d8227dfd94 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio.h
@@ -8,4 +8,10 @@
#define CROS_GPIO_DEVICE_NAME "INT34C5:00"
+/* Enable GPIO community power management configuration */
+#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \
+ MISCCFG_GPPGCBDPCGEN | MISCCFG_GPSIDEDPCGEN | \
+ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
#endif
diff --git a/src/soc/intel/xeon_sp/include/soc/gpio.h b/src/soc/intel/xeon_sp/include/soc/gpio.h
index 6e85d4e021..04eb9ae31c 100644
--- a/src/soc/intel/xeon_sp/include/soc/gpio.h
+++ b/src/soc/intel/xeon_sp/include/soc/gpio.h
@@ -6,4 +6,10 @@
#include <soc/lewisburg_pch_gpio_defs.h>
#include <intelblocks/gpio.h>
+/*
+ * XEON SP series doesn't support dynamic GPIO PM hence GPIO community
+ * MISCCFG register doesn't have PM bits
+ */
+#define MISCCFG_GPIO_PM_CONFIG_BITS 0
+
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 22:32:28 +0000