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-rw-r--r--src/soc/intel/apollolake/bootblock/bootblock.c28
-rw-r--r--src/soc/intel/apollolake/include/soc/mmap_boot.h22
-rw-r--r--src/soc/intel/apollolake/mmap_boot.c7
-rw-r--r--src/soc/intel/common/block/fast_spi/fast_spi.c25
-rw-r--r--src/soc/intel/common/block/include/intelblocks/fast_spi.h4
-rw-r--r--src/soc/intel/skylake/bootblock/cpu.c27
6 files changed, 31 insertions, 82 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 2c98be4fae..5c059d97c2 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -16,17 +16,14 @@
*/
#include <arch/cpu.h>
#include <bootblock_common.h>
-#include <cpu/x86/mtrr.h>
#include <device/pci.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/pcr.h>
#include <intelblocks/rtc.h>
#include <intelblocks/systemagent.h>
-#include <lib.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/gpio.h>
-#include <soc/mmap_boot.h>
#include <soc/systemagent.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
@@ -69,29 +66,6 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
bootblock_main_with_timestamp(base_timestamp);
}
-static void cache_bios_region(void)
-{
- int mtrr;
- size_t rom_size;
- uint32_t alignment;
-
- mtrr = get_free_var_mtrr();
-
- if (mtrr == -1)
- return;
-
- /* Only the IFD BIOS region is memory mapped (at top of 4G) */
- rom_size = get_bios_size();
-
- if (!rom_size)
- return;
-
- /* Round to power of two */
- alignment = 1 << (log2_ceil(rom_size));
- rom_size = ALIGN_UP(rom_size, alignment);
- set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT);
-}
-
static void enable_pmcbar(void)
{
device_t pmc = PCH_DEV_PMC;
@@ -125,7 +99,7 @@ void bootblock_soc_early_init(void)
fast_spi_early_init(PRERAM_SPI_BASE_ADDRESS);
- cache_bios_region();
+ fast_spi_cache_bios_region();
/* Initialize GPE for use as interrupt status */
pmc_gpe_init();
diff --git a/src/soc/intel/apollolake/include/soc/mmap_boot.h b/src/soc/intel/apollolake/include/soc/mmap_boot.h
deleted file mode 100644
index 80f25a9147..0000000000
--- a/src/soc/intel/apollolake/include/soc/mmap_boot.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_APOLLOLAKE_MMAP_BOOT_H__
-#define __SOC_APOLLOLAKE_MMAP_BOOT_H__
-
-size_t get_bios_size(void);
-
-#endif /* __SOC_APOLLOLAKE_MMAP_BOOT_H__ */
diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c
index 598c068428..db13cba62f 100644
--- a/src/soc/intel/apollolake/mmap_boot.c
+++ b/src/soc/intel/apollolake/mmap_boot.c
@@ -23,7 +23,6 @@
#include <console/console.h>
#include <fmap.h>
#include <intelblocks/fast_spi.h>
-#include <soc/mmap_boot.h>
/*
* BIOS region on the flash is mapped right below 4GiB in the address
@@ -133,9 +132,3 @@ const struct cbfs_locator cbfs_master_header_locator = {
.name = "IAFW Locator",
.locate = iafw_boot_region_properties,
};
-
-size_t get_bios_size(void)
-{
- bios_mmap_init();
- return car_get_var(bios_size);
-}
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 603af16881..a53499eba6 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -18,8 +18,10 @@
#include <device/pci_def.h>
#include <commonlib/helpers.h>
#include <console/console.h>
+#include <cpu/x86/mtrr.h>
#include <fast_spi_def.h>
#include <intelblocks/fast_spi.h>
+#include <lib.h>
#include <soc/intel/common/spi_flash.h>
#include <soc/pci_devs.h>
#include <spi_flash.h>
@@ -175,6 +177,29 @@ size_t fast_spi_get_bios_region(size_t *bios_size)
return bios_start;
}
+void fast_spi_cache_bios_region(void)
+{
+ int mtrr;
+ size_t bios_size;
+ uint32_t alignment;
+
+ mtrr = get_free_var_mtrr();
+
+ if (mtrr == -1)
+ return;
+
+ /* Only the IFD BIOS region is memory mapped (at top of 4G) */
+ fast_spi_get_bios_region(&bios_size);
+
+ if (!bios_size)
+ return;
+
+ /* Round to power of two */
+ alignment = 1 << (log2_ceil(bios_size));
+ bios_size = ALIGN_UP(bios_size, alignment);
+ set_var_mtrr(mtrr, 4ULL*GiB - bios_size, bios_size, MTRR_TYPE_WRPROT);
+}
+
/*
* Program temporary BAR for SPI in case any of the stages before ramstage need
* to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI
diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
index e4bddc4e45..6294001d23 100644
--- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h
+++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
@@ -57,6 +57,10 @@ void fast_spi_set_strap_msg_data(uint32_t soft_reset_data);
*/
size_t fast_spi_get_bios_region(size_t *bios_size);
/*
+ * Cache the memory-mapped BIOS region as write-protect type.
+ */
+void fast_spi_cache_bios_region(void);
+/*
* Program temporary BAR for FAST_SPI in case any of the stages before ramstage
* need to access FAST_SPI MMIO regs. Ramstage will assign a new BAR during PCI
* enumeration. Also, Disable the BIOS write protect and Enable Prefetching and
diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index 040e847e6c..dd51104b4d 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -17,10 +17,8 @@
#include <arch/io.h>
#include <console/console.h>
#include <cpu/intel/microcode/microcode.c>
-#include <cpu/x86/mtrr.h>
#include <delay.h>
#include <intelblocks/fast_spi.h>
-#include <lib.h>
#include <reset.h>
#include <soc/bootblock.h>
#include <soc/cpu.h>
@@ -86,32 +84,9 @@ static void set_flex_ratio_to_tdp_nominal(void)
soft_reset();
}
-static void cache_bios_region(void)
-{
- int mtrr;
- size_t rom_size;
- uint32_t alignment;
-
- mtrr = get_free_var_mtrr();
-
- if (mtrr == -1)
- return;
-
- /* Only the IFD BIOS region is memory mapped (at top of 4G) */
- rom_size = CONFIG_ROM_SIZE;
-
- if (!rom_size)
- return;
-
- /* Round to power of two */
- alignment = 1 << (log2_ceil(rom_size));
- rom_size = ALIGN_UP(rom_size, alignment);
- set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT);
-}
-
void bootblock_cpu_init(void)
{
- cache_bios_region();
+ fast_spi_cache_bios_region();
/* Set flex ratio and reset if needed */
set_flex_ratio_to_tdp_nominal();
intel_update_microcode_from_cbfs();