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-rw-r--r--src/soc/amd/stoneyridge/bootblock/bootblock.c2
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h1
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c13
3 files changed, 1 insertions, 15 deletions
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index 3eff5eb0dc..fafaf079ce 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -75,8 +75,6 @@ void bootblock_soc_early_init(void)
bootblock_fch_early_init();
post_code(0x90);
- if (CONFIG_STONEYRIDGE_UART)
- configure_stoneyridge_uart();
}
/*
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 6dea0c6864..bdcb38fa8d 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -353,7 +353,6 @@ struct stoneyridge_aoac {
void enable_aoac_devices(void);
void sb_enable_rom(void);
-void configure_stoneyridge_uart(void);
void configure_stoneyridge_i2c(void);
void sb_clk_output_48Mhz(void);
void sb_disable_4dw_burst(void);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index cf059a46b2..55e39569d0 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -36,9 +36,7 @@
* Table of devices that need their AOAC registers enabled and waited
* upon (usually about .55 milliseconds). Instead of individual delays
* waiting for each device to become available, a single delay will be
- * executed at configure_stoneyridge_uart(). All other devices need only
- * to verify if their AOAC is already enabled, and do a minimal delay
- * if needed.
+ * executed.
*/
const static struct stoneyridge_aoac aoac_devs[] = {
{ (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2),
@@ -331,15 +329,6 @@ void enable_aoac_devices(void)
} while (!status);
}
-void configure_stoneyridge_uart(void)
-{
- /* Set the GPIO mux to UART */
- write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0);
- write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0);
- write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0);
- write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0);
-}
-
void sb_pci_port80(void)
{
u8 byte;